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24小时计时时钟
实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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pid-vhdl
基于vhdl的pid控制器设计，可以用quartus等软件实现。数字控制系统pid设计源代码。(Pid controller based on VHDL design, can use the quartus software implementation, etc. Digital pid control system design of source co)
- 2014-05-12 21:15:37下载
- 积分：1
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liushuideng
使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)
- 2013-08-31 15:23:06下载
- 积分：1
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十字路
控制路线和街道交叉口的简单程序，路线优先，街道上有车辆检测器；
- 2022-03-04 07:16:26下载
- 积分：1
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pipeline_FPGA
FPGA流水线设计的资料，可以作为学习FPGA开发并行操作的一个经典教材，具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分：1
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简单的APB I2S接口
简单的apb i2s接口，verilog代码，包括rtl实现和testbench(apb i2s interface . coded by Verilog. including rtl and testbench)
- 2019-01-18 16:52:05下载
- 积分：1
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OQPSK
OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)
- 2021-03-09 20:39:27下载
- 积分：1
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这个程序可以帮助转换成BCD码excess3代码，完美…
this the program which can help to convert bcd code to excess3 code,the perfect circuitary has been given in this document which will lead you to understand it more properly.Reference is taken from morris mano book of digital electronics.This program can work on quatrus without any trouble.this is also used to make a final year -this is the program which can help to convert bcd code to excess3 code,the perfect circuitary has been given in this document which will lead you to understand it more properly.Reference is taken from morris mano book of digital electronics.This program can work on quatrus without any trouble.this is also used to make a final year
- 2022-03-16 21:25:25下载
- 积分：1
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m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2022-02-02 08:36:01下载
- 积分：1
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提供的i2c控制IP核 master
open cores 提供的i2c控制IP核 可直接在FPGA上使用。并带有相关的测试程序(endorsed by the i2c controller IP provided by the open cores on the FPGA. With the relevant test procedures)
- 2012-05-23 10:31:27下载
- 积分：1
