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verilog_show10
基于VHDL编写的10进制显示输出，基于16进制的10进制控制，适合初学者(VHDL-based display output written in decimal, hexadecimal, 10 hexadecimal-based control, suitable for beginners)
- 2011-11-21 14:29:56下载
- 积分：1
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Clutter-Filtering-
。给出了时域滤波的基本原理以及通常采用的
IIR 椭圆地物杂波滤波器的设计方法。重点研究了回归滤波器这一时域滤波算
法。从正交多项式的拟合出发，给出了回归滤波器抑制地物杂波的基本原理及
其滤波实现过程。通过对回归滤波器的计算复杂度的研究，寻找使回归滤波器
计算量最小的正交多项式。分析了回归滤波器频率响应特性，比较了回归滤波
器与IIR 椭圆地物杂波滤波器的计算复杂度。利用仿真的雷达信号，分析了回
归滤波器的地物杂波抑制性能。回归滤波器实际上是一高通滤波器，它在滤掉
低频地物杂波的同时，对落在滤波器阻带内的天气回波信号同样会造成衰减。
在天气回波信号谱宽固定的情况下，通过改变天气回波信号的平均多普勒频率，
分析了回归滤波器对它的衰减情况。在基于一组实际采集的雷达信号的基础上，
给出了回归滤波器的地物杂波抑制比随着滤波器阶数的变化情况。(Firstly, this dissertation introduces the research background and significance of
ground clutter suppression, analyzes the characteristics of the ground clutter and
weather signals in the Doppler weather radars and simulates Doppler radar echo
signals (It includes ground clutter, weather echo signals and the mixture of them).
The simulated signals are used later to study the time and frequency domain ground
clutter suppression.
Secondly, this dissertation talks about the time domain filtering, gives the basic
theory of time domain filtering and describes the design method of the usually used
fifth-order elliptic infinite impulse response (IIR) ground clutter filter. In the time
domain, the work focuses on the regression filter. From the orthogonal polynomials
fit, this dissertation gives the basic theory of the regression filter for ground clutter
suppression and the filtering process using a regression filter. Through the study of
the computational complexity of regression)
- 2012-07-09 22:12:11下载
- 积分：1
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Viterberi 解码器
Viterberi 解码器使用 vhdl 编程实现将被用于制作增强功能
- 2023-03-06 21:00:04下载
- 积分：1
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FPGA
基于FPGA与LM4550B的AC97软声卡VHDL语言驱动，版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0
- 2022-10-28 20:25:03下载
- 积分：1
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用VHDL和verilog实现的四人抢答器
用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
- 2023-07-17 00:15:04下载
- 积分：1
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UG586-7SeriesDMIUserGuide
UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )(UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB ))
- 2015-02-05 20:02:21下载
- 积分：1
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16/64 点 FFT
这是通过使用 VHDL 代码的 FFT 库函数。它可以切换的 FFT 16 点和 64 点之间的长度。它包含蝴蝶、捻因子、 ROM、 RAM 和等等。它可以成功运行在 Quartus 2 或其他软件上。
- 2022-03-13 13:35:13下载
- 积分：1
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QPSK
用Verilog语言实现QPSK调制，QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。
(Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.)
- 2011-01-24 17:46:44下载
- 积分：1
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FPGA_PSK
说明： 可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
- 2019-05-09 16:29:17下载
- 积分：1
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verilog HDL语言，对于超大规模集成电路开发学习非常有好处
verilog HDL语言，对于超大规模集成电路开发学习非常有好处-verilog HDL language, for ultra-large-scale integrated circuits are very beneficial to the development of learning
- 2022-12-28 13:40:09下载
- 积分：1
