登录
首页 » VHDL » 简易cpu的设计

简易cpu的设计

于 2022-03-12 发布 文件大小:1.57 kB
0 51
下载积分: 2 下载次数: 1

代码说明:

计算机组成原理的课程设计作业,用vhdl语言写了一个简易的cpu,包括寄存器,存储器等原件,完全用代码写成,没有直接用原件去连接,有助于我们很好的学习vhdl。   这是一个cpu的连接代码,并没有各种原件的代码 ,因为各个原件代码很简单就没上传

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • PID
    用Verilog HDL编写的PID程序代码,成功调试,运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)
    2012-03-09 11:18:17下载
    积分:1
  • 1 前大灯可以随意打开和关闭; 2 当汽车左转弯的时候,前左转向灯闪烁,同时左后灯的3盏灯由右往左闪烁; 3 当汽车有转弯的时候,前右转向灯闪烁,同时右...
    1 前大灯可以随意打开和关闭; 2 当汽车左转弯的时候,前左转向灯闪烁,同时左后灯的3盏灯由右往左闪烁; 3 当汽车有转弯的时候,前右转向灯闪烁,同时右后灯的3盏灯有左往右闪烁; 4 当汽车减速或紧急刹车的时候,左后灯和右后等同时闪烁; 5 当汽车在左转弯的同时减速,则前左转向灯闪烁,左后灯的3盏灯由右往左闪烁,同时右后灯都点亮。 6 当汽车在左转弯的同时减速,则前右转向灯闪烁,右后灯的3盏灯有左往右闪烁,同时左后灯都点亮。 -a former headlamps can be opened and closed at will; 2 when the vehicle made a left turn when the former left to lights flickered. Left lights while the three lights flashing from right-go left; 3 when the vehicle is making a turn when a right turn to the former lights flickered. Right after the lights while the three lights are blinking right and left; 4 when the vehicle deceleration or when the emergency brake, Left and right after the lights blink, and so on; 5 when the vehicle made a left turn at the same time to slow down, and then to the left before the lights flickered. Left lights three lights flashing from right-go left, right after the lights are lit. 6 when a car made a left turn at the same time to slow down, and then right before the lights to flick
    2022-03-04 04:27:43下载
    积分:1
  • Verilog digital system design tutorials, e
    Verilog数字系统设计教程,作者夏宇闻电子书籍-Verilog digital system design tutorials, e-books by XIA Yu-Wen
    2023-03-21 06:15:07下载
    积分:1
  • ControlUnit
    Control Unit VHDL code. Xilinx Spartan 3E board
    2012-03-15 13:29:40下载
    积分:1
  • AD
    说明:  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)
    2020-12-19 17:09:10下载
    积分:1
  • gff_int_mul
    application of a galois field multiplication and normal multiplication
    2008-05-28 16:23:11下载
    积分:1
  • m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过...
    m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
    2022-02-02 08:36:01下载
    积分:1
  • transmittermegafunction
    lvds transmitter megafunction (lvds transmitter megafunction)
    2008-03-09 19:40:03下载
    积分:1
  • hapf
    单相混合有源电力滤波器的设计与控制,在matlab中的仿真模型,功能效果很好。(The design and control of single-phase hybrid active power filter in matlab simulation model, the function works well.)
    2012-12-11 16:17:23下载
    积分:1
  • msp430x41x
    低电源电压范围为1.8 V至3.6 V 超低功耗: - 主动模式:280μA,在1 MHz,2.2伏 - 待机模式:1.1μA - 关闭模式(RAM保持):0.1μA 五省电模式 欠待机模式唤醒 超过6微秒 16位RISC架构, 125 ns指令周期时间 12位A/ D转换器具有内部 参考,采样和保持,并 AutoScan功能 16位Timer_B随着三† 或七‡ 捕捉/比较随着阴影寄存器 具有三个16位定时器A 捕捉/比较寄存器 片上比较器 串行通信接口(USART), 选择异步UART或 同步SPI软件: - 两个USART(USART0 USART1)的† - 一个USART(USART0)‡ 掉电检测 电源电压监控器/监视器 可编程电平检测 串行板载编程, 无需外部编程电压 安全可编程代码保护 融合(Low Supply-Voltage Range, 1.8 V to 3.6 V Ultralow-Power Consumption: − Active Mode: 280 µ A at 1 MHz, 2.2 V − Standby Mode: 1.1 µ A − Off Mode (RAM Retention): 0.1 µ A Five Power Saving Modes Wake-Up From Standby Mode in Less Than 6 µ s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature 16-Bit Timer_B With Three† or Seven‡ Capture/Compare-With-Shadow Registers 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software: − Two USARTs (USART0, USART1)† − One USART (USART0)‡ Brownout Detector Supply Voltage Supervisor/Monitor With Programmable Level Detection Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse)
    2012-05-31 15:26:33下载
    积分:1
  • 696518资源总数
  • 104298会员总数
  • 46今日下载