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OFDM_TX_CR802.11-master
OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)
- 2018-11-15 17:03:03下载
- 积分:1
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SPI_Master
此代码是SPI接口的Master的Verilog源代码,经上板测试是没有问题的,请大家放心使用
(This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use)
- 2021-02-25 09:19:38下载
- 积分:1
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ABencode
FPGA实现增量式光栅尺正交脉冲解码,基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)
- 2020-11-21 20:59:36下载
- 积分:1
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13_usb_test
利用FPGA硬件编程语言Verilog实现USB通信开发(Realization of USB communication development by using FPGA hardware programming language Verilog)
- 2018-08-09 10:08:00下载
- 积分:1
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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分:1
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ddr3control
8位突发长度,一次64bit数据读写,MIG核(DDR3 controll implimention)
- 2021-05-07 13:58:36下载
- 积分:1
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liyuanlnx_IP_RAM
FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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vhdl.9up
have a good documenty
- 2010-04-15 14:26:07下载
- 积分:1
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用FPGA实现电子钟
这是用verilog语言所编写的一个数字时钟程序,并在FPGA开发板上运行成功。相比于其他语言,veilog语言更加简洁,因此此程序包括各个模块,可以在开发板上仿真。
- 2022-01-21 00:24:14下载
- 积分:1
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Get-20-point
this program get 20 point from user and draw functions.
- 2014-01-09 03:25:06下载
- 积分:1