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移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件
移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents
- 2022-06-19 21:07:11下载
- 积分：1
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this a fpga sparttan 3e based project in which
i have made a game based on vg...
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for ps/2 interface .
- 2022-05-21 12:25:58下载
- 积分：1
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Regs
说明： 一个小寄存器堆，使用参数化编程，附有仿真代码，可直接在vivado（2018.2版本及以后）上运行(A small register heap, using parametric programming)
- 2019-04-03 14:19:55下载
- 积分：1
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float_mult32x32.v
verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
- 2018-07-19 17:33:42下载
- 积分：1
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摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL
语言编写控制程序，利用CPLD的可重复编...
摘要：本文主要介绍以CPLD 芯片进行十字路口的交通灯的设计，用CPLD 作为交通灯控制器的主控芯片，采用VHDL
语言编写控制程序，利用CPLD的可重复编程和在动态系统重构的特性，大大地提高了数字系统设计的灵活性和通用性。
关键词：CPLD；VHDL；交通灯控制器
中图分类号：TP39
Abstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by-Abstract: This paper introduces the CPLD chip to the traffic lights at the crossroads of design, traffic lights with CPLD as the master controller chip, the use of VHDL language control procedures, the use of CPLD re-programming and dynamic system reconfiguration in the features greatly enhance the digital system design flexibility and versatility. Keywords: CPLD VHDL traffic lights controller CLC number: TP39 Abstract: This paper introduces the electronic-traffic lamp, which is based on the VHDL and is completed by
- 2022-05-20 22:55:36下载
- 积分：1
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FPGA的设计流程手册
FPGA设计流程指南
介绍基本的设计方法-FPGA Design Process Manual
- 2022-08-14 04:24:11下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入
熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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SDRAM
基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
- 2018-01-16 11:24:03下载
- 积分：1
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pex8311代码实现
pex8311代码实现 altera的fpga 代码编程 实现本地读写 pex8311_test
- 2022-01-28 06:56:26下载
- 积分：1
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一个小液晶的程序。我没写。我只负责设计。
一个液晶灯的小程序。我没有写信。我只负责调试。适用于ACEXEP1K30QC208-3。我运行模拟器，标记连接销。我接下来在电路板上试了试，没有问题。实验中使用的板兄弟把CLK1的TESTOUT3改成了合唱或0。新人在线帮助是每个人的责任。
- 2022-02-09 15:34:18下载
- 积分：1
