scramble
于 2022-03-03 发布
文件大小:296.63 kB
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代码说明:
VHDL编写加扰和解扰程序,程序连在一起仿真正确,并通过下板子抓数据验证程序没问题-Write scrambling and descrambling program, VHDL program together properly simulation, and data validation procedures is caught by the board no problem
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