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Program to implement convolution of two signals.
Program to implement convolution of two signals.
- 2023-04-30 22:25:04下载
- 积分：1
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2018全国大学生FPGA大赛封闭测试上机题
说明： 2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目，以及自己编写的verilog和testbench，欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)
- 2020-11-23 22:39:33下载
- 积分：1
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wireless_communication_FPGA
数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)
- 2015-01-30 22:03:45下载
- 积分：1
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rfid new code
说明： In the data management system a significant role of the Data link layer is to convert the unreliable physical link between reader and tag into a reliable link. Therefore, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. In addition for reader to communicate with the multiple tags, an anti-collision technique is required. The technique is to coordinate the communication between the reader and the tags. The common deterministic anti-collision techniques are based on the Tree algorithm such as the Binary Tree and the Query Tree algorithms.
- 2019-04-30 16:54:27下载
- 积分：1
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quartusandmodelsim
本文档对quartus与modelsim运用操作描述十分详细，对初学者，会有很大帮助！(Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!)
- 2010-08-30 23:51:02下载
- 积分：1
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FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的...
FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的-FPGA experiment, realized the buzzer sounded a different tone, the use of keys, it is fun
- 2022-07-24 17:58:54下载
- 积分：1
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八线-三线优先编码器
基本的操作代码,a0-a7是八个信号输入端，a7的优先级最高，a0的优先级最低，当a7输入低电平0时，其他输入无效，编码输出y2y1y0=111；如果a7无效，而a6有效，则y2y1y0=110；
- 2023-05-02 18:40:03下载
- 积分：1
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VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验...
VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
- 2022-05-08 02:59:08下载
- 积分：1
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dma_hussam
verilog code for dma
- 2021-04-24 19:09:04下载
- 积分：1
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shizhong
VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分：1
