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通过VHDL语言的例子,FPGA原型的VHDL例子(chapter3-part1)
应用背景关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2023-04-20 18:05:04下载
- 积分:1
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429recive
实现FPGA接收429板卡发送的信号,并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)
- 2015-11-26 11:18:19下载
- 积分:1
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Sdram_Control_4Port
使用verilog HDL写的sdram(SDR)的控制器源代码,具有很好的可移植性,试验的例子已经通过QuartusII 9.0编译通过,可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)
- 2012-05-14 15:36:09下载
- 积分:1
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IIC
fpga实现的IIC通信的例程,注释很详细(fpga implementation of serial communication routines, comments in great detail)
- 2021-03-24 16:29:15下载
- 积分:1
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design of 1-bit memory using cmos logic
&单元格
- 2022-02-04 02:43:34下载
- 积分:1
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Verilog
32位存储器Verilog附带test文件,可以在modulesim仿真
还有加法、减法器,译码器等常用Verilog器件,都附带仿真test。(Memory test with Verilog)
- 2010-07-17 17:20:00下载
- 积分:1
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polyphaseFIR_1v0
polyphase fir dilter
- 2016-02-19 21:32:07下载
- 积分:1
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cic_dec_8_three
CIC 文件的VHDL
cic_dec_8_three
CIC 文件的VHDL-cic_dec_8_threeCIC documents VHDL
- 2023-03-30 12:50:03下载
- 积分:1
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performance with rayleigh
说明: matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分:1
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xilinx-timing-constrains
ISE时序约束笔记——Global Timing Constraints,这个文档中详细介绍了如何使用ISE中约束工具和原理,对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)
- 2012-04-16 11:08:45下载
- 积分:1