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GBT-15946-2008GPIB
GBT 15946-2008 GPIB可编程仪器标准数字接口的高性能协议 概述 (GBT 15946-2008 GPIB Programmable Instruments standard digital interface for high-performance protocol Overview)
- 2012-08-30 11:49:29下载
- 积分:1
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SDR
直接序列扩频通信的Verilog仿真代码,在Quartus II中实现。(Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.)
- 2011-01-16 12:18:18下载
- 积分:1
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Xilinx vivado authoritative course
说明: Xilinx vivado 权威教程,清华大学出版社出版,何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)
- 2019-02-19 20:37:09下载
- 积分:1
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sos_module
用FPGA实现sos摩尔密码,即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”,“画”和“间隔”。而 control_module.v 是一个简单的定时触发器,每一段时间都会使能sos_module.v。(Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each period of time will enable sos_module.v.)
- 2016-09-20 16:26:29下载
- 积分:1
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sha1_v01
说明: SHA-1加密算法的IP核,内涵文档,仿真测试文件(SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file)
- 2008-10-15 09:05:58下载
- 积分:1
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利用分频可以产生一系列脉冲,根据输入脉冲的不同决定你得到的一系列脉冲频率...
利用分频可以产生一系列脉冲,根据输入脉冲的不同决定你得到的一系列脉冲频率-The use of sub-band can produce a series of pulses, according to input pulse of different decisions you have a series of pulse frequency
- 2023-08-19 18:35:03下载
- 积分:1
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arm7
ARM7 VERILOG源码,非常精简,3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)
- 2009-12-02 10:57:51下载
- 积分:1
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Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开...
Altera的CycloneIII Start Board,使用的PFGA是3C25,包括原理图和PCB,用Cadence Allegro打开-Altera
- 2022-10-05 01:50:03下载
- 积分:1
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simple code based on verilog
shifter , cla ,clg , ALU , PC
simple code based on verilog
shifter , cla ,clg , ALU , PC
- 2022-03-04 03:11:05下载
- 积分:1
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MUX
Multipleksor
3 to 1 - 3x1bit in, 1x1bit out
- 2013-09-18 16:21:25下载
- 积分:1