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电子时钟
基于DE2-115的数字时钟
1.液晶显示,数码管显示
2.整点报时
3.闹钟
4.设置时间
5.设置闹钟(Digital clock based on DE2-115
1. LCD display, digital tube display
2. whole point
3. alarm clock
4. setting time
5. set the alarm clock)
- 2021-03-06 23:39:29下载
- 积分:1
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AD_FIFO
简单的Verilog程序,针对音频实验板的AD到DA调通试验,下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform.
Please configure it according to the test environment before download and implement the program to FPGA)
- 2013-01-26 00:47:37下载
- 积分:1
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PID
利用VHDL语言实现PID控制,已经过调试验证。(Using VHDL language to implement PID control)
- 2018-04-30 16:33:39下载
- 积分:1
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Building the CPU datapath
Building the CPU datapath
- 2022-07-24 12:10:47下载
- 积分:1
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240188modified-rom-based-logic
Modified rom based logic
- 2016-04-01 09:48:45下载
- 积分:1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分:1
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textiowrite
quartus ii 环境下,一个完整的利用TEXTIO仿真的源代码,包括读数据文件和输出数据到文件。(Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.)
- 2014-02-03 23:56:30下载
- 积分:1
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一位LED显示的VHDL程序,挺简单的,买的开发板里面带的
一位LED显示的VHDL程序,挺简单的,买的开发板里面带的-An LED display of the VHDL program, quite simply, to buy development board inside the zone
- 2023-07-18 00:45:02下载
- 积分:1
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ConvolutionWithViterbiDecoding
QPSK调制下的(5,7)卷积码的编码和维特比译码与BPSK调制下(5,7)卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)
- 2020-12-12 20:09:15下载
- 积分:1
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FPGA的并行流水线的AES-GCM核心100G以太网应用
应用背景在本文中,我们提出了一种高效的设计方法在可重构硬件设备中实现GCM结合认证加密AES。由于四AES内核和四binaryfield复制我们能演示如何打破该100Gbps的速度必将在FPGA。为了减少的在Ghash操作关键路径,四级流水线已被插入在广发(2128)乘法。这个最后的GCM的架构依赖于一个4×4建筑实现了在Xilinx Virtex-5器件119gbps。关键技术即将推出的IEEE以太网标准的重点将提供的数据传输带宽的100Gbit /美国目前,最快的加密原始批准的美国国家标准与技术研究所,结合数据加密和身份认证,是伽罗瓦/计数器模式(GCM)操作。如果可行性,提高速度的GCM到100Gbit/s的ASIC技术已经表明,在GCM FPGA实现安全100G以太网网络系统出现了一些重要的结构问题。在本文中,我们报告一个高效的FPGA架构该模式结合AES分组密码。与四流水线并行AES-GCM芯我们可以要达到新的以太网标准要求的速度。此外,时间关键二进制字段乘法的认证过程依赖于四个流水线2 Karatsuba—人乘子。
- 2022-04-01 01:49:49下载
- 积分:1