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EDAcodelock
能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能，并能更改使用密码，还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)
- 2009-05-07 09:44:30下载
- 积分：1
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采用硬件描述语言Verilog HDL实现人回答功能，H.
用verilog hdl硬件描述语言实现多人抢答器功能，有计时，计分，报警等功能。-Using hardware description language verilog hdl people realize Answer feature, have timing, scoring and alarm functions.
- 2022-03-17 02:15:20下载
- 积分：1
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20190717 - Copy
this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分：1
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这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com...
这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
- 2022-05-06 16:15:30下载
- 积分：1
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AM-modulated-learning-ladder
AM modulated learning ladder
- 2015-07-15 09:42:45下载
- 积分：1
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一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了...
一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms
- 2022-08-14 17:54:21下载
- 积分：1
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11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合...
11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
- 2022-10-31 17:45:02下载
- 积分：1
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DC-Voltmeter
Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage
- 2013-01-07 22:52:54下载
- 积分：1
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UART Basic, hardwired RS232 UART.
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- 2023-05-28 14:35:03下载
- 积分：1
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Vpwm
按键可调占空比的PWM波产生程序。语言：VHDL(Button adjustable duty cycle of the PWM wave generator. Language: VHDL)
- 2013-07-30 12:30:58下载
- 积分：1
