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verilogCRC32
32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分：1
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iic_sci
FPGA编程，经过团体奋战完成，全是底层的IIc和sci通信，完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)
- 2014-12-23 09:32:54下载
- 积分：1
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polyphaseFIR_1v0
polyphase fir dilter
- 2016-02-19 21:32:07下载
- 积分：1
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ComChange-12061629
说明： 并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分：1
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ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口...
ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
- 2022-05-25 15:09:52下载
- 积分：1
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LDPC_Encoder
verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分：1
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vga_interface_requiring_core_regeneration
vga interface with text rom. font size 80x40. core need core regeneration.
- 2013-05-19 02:09:10下载
- 积分：1
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FPGA_Seg7_dsp
关于VHDL和verilog的数码管显示程序，写的很好，值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)
- 2014-08-01 11:00:51下载
- 积分：1
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Idddc_30mF
中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号
(IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)
- 2012-07-25 23:56:30下载
- 积分：1
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地铁售票系统，基于VHDL，可实现站点设置，站点选择，选择购票数量，找零等一系列功能。...
地铁售票系统，基于VHDL，可实现站点设置，站点选择，选择购票数量，找零等一系列功能。-Metro ticketing system, based on VHDL, allows site settings, site selection, choose the number of tickets, Keep the change and a series of functions.
- 2022-02-16 02:43:18下载
- 积分：1
