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ref-sdr-sdram-verilog
sdram控制器的开发程序，还有文档，可以参考以下(SDRAM controller development process, there is a document, you can refer to the following)
- 2008-06-13 22:15:41下载
- 积分：1
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240188modified-rom-based-logic
Modified rom based logic
- 2016-04-01 09:48:45下载
- 积分：1
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产生伪的VHDL语言程序
伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
- 2022-02-05 15:49:12下载
- 积分：1
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count4
这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)
- 2013-08-04 09:45:07下载
- 积分：1
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VHDL版的C51核(MC8051)
VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)
- 2022-06-19 21:32:45下载
- 积分：1
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Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.
数字频率计VHDL程序与仿真
文件名：plj.vhd。
--功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的
--高4位进行动态显示。小数点表示是千位，即KHz。
-Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for the high dynamic display. Decimal point that is 1000, or KHz.
- 2022-08-04 07:22:59下载
- 积分：1
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vgachar
VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)
- 2012-05-31 10:35:14下载
- 积分：1
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4jieshuzilboqi
四阶数字滤波器 用不同的算法设计数字滤波器，并且有详细的是用方法(Fourth-order digital filter design with a different digital filter algorithms and a detailed method is)
- 2011-04-25 18:18:16下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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sportswatch
完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)
- 2009-12-09 11:25:27下载
- 积分：1
