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digital-PLL
收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。(Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.)
- 2015-02-11 10:39:31下载
- 积分：1
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FPGA7人表决器
–ABCDE五路输入表示五人的选择，同意为1，不同意为0，以开关形式实现
–有半数以上同意绿灯亮，否则红灯亮。即分别对应输出Y、R为1或0
–参考仿真结果图：10ns|20ns|30ns|40ns|50ns
- 2022-10-01 22:45:03下载
- 积分：1
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CAM
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory, associative storage, or associative array, although the last term is more often used for a programming data structure.
- 2014-12-06 00:33:45下载
- 积分：1
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codic
8级cordic 算法verilog (8 cordic algorithm verilog)
- 2013-08-21 11:31:46下载
- 积分：1
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大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。...
大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL description language. Rom which documents can be automatically generated using lpm_megcore.
- 2022-03-05 14:52:20下载
- 积分：1
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DDS
基于FPGA器件的DDS设计实现中的一个核心部分就是波形存储表的设计。首先采用LPM_ROM和
VHDL选择语句这两种方法进行波形存储表的设计和比较分析 然后考虑到硬件资源的有限性及DDS的精度要
求,对这两种方法的程序进行了优化 最后对这两种方法设计的程序进行仿真和硬件调试。结果表明:采用这两种
方法都能有效地实现DDS中波形存储表的设计。
(DDS-based FPGA devices designed to achieve one of the core of the waveform is stored in table design. First of all, choose to adopt LPM_ROM and VHDL statements of these two methods for the design waveform storage tables and comparative analysis and then, taking into account the limited hardware resources and the accuracy of DDS, the two methods to optimize the process the last of these two methods of process design simulation and hardware debugging. The results showed that: the use of these two methods are all effective ways to achieve the DDS waveform stored in the table design.)
- 2009-05-24 10:56:30下载
- 积分：1
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yuandaima
以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分：1
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DA_Test
说明： 基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)
- 2020-03-29 22:36:29下载
- 积分：1
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Beamforming
基于FPGA的波束形成，包括ad转换，数据存储等部分。。(FPGA-based beamforming, including ad conversion, data storage and other parts. .)
- 2016-04-25 11:12:30下载
- 积分：1
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MIPSTOP
misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
