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FpgaFskMod
基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)
- 2021-05-12 17:30:03下载
- 积分：1
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FpMultiplier
说明： 可调矩阵，最大32*32位浮点数乘法矩阵及仿真。(32*32 floating multiplication matrix)
- 2021-02-09 00:25:23下载
- 积分：1
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本例为DAC0832接口电路VHDL原代码
本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code
- 2022-08-14 02:36:10下载
- 积分：1
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nco11000
实现输入一正弦波和噪声的叠加，介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)
- 2010-05-16 14:19:53下载
- 积分：1
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通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成...
通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation
- 2022-03-14 12:44:53下载
- 积分：1
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VHDL的食谱
The VHDL Cookbook
First Edition
July, 1990
Peter J. Ashenden
Dept. Computer Science
University of Adelaide
South Australia
- 2023-02-13 13:30:04下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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xapp1014-xilinx-sdi
用fpga实现SDI，每一步都很清楚 搞视频的可以参考(Fpga realization of SDI, each step are clearly engaged in the video can refer to)
- 2020-11-10 19:19:46下载
- 积分：1
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gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分：1
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VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分：1
