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ByteBlasterII 下载线的制作
ByteBlasterII 下载线的制作-Download ByteBlasterII production line
- 2023-03-03 07:20:04下载
- 积分：1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分：1
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zidongmen1
控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分：1
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FSK
2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分：1
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VHDL
VHDL-2008
Just the New Stuff
Peter J. Ashenden
Consultant
Ashenden Designs
- 2022-03-31 09:30:59下载
- 积分：1
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2
说明： Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes.
The representation step specifies the mapping the phenotypes onto a set of genotypes.
Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space.
Chromosome, and individual can be used for points in the genotye space.
Elements of a chromosome are called genes. A value of a gene is called an allele.
Variation Operators
The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.
- 2014-12-22 22:54:47下载
- 积分：1
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Chapter11-13
第十一章到第十三章的代码
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。(Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.)
- 2009-11-17 13:57:09下载
- 积分：1
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FSM_test for textbanch in vhdl
FSM_test for textbanch in vhdl-FSM_test
- 2022-03-26 05:01:26下载
- 积分：1
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sch_tbf
Token Bucket Filter queue.
- 2013-05-06 11:34:24下载
- 积分：1
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Flicker_LED
It s Flicker_LED code.Verilog for MaxV.
- 2013-08-08 10:16:32下载
- 积分：1
