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三维小波变换
三维离散小波变换的代码
- 2022-03-06 08:50:16下载
- 积分:1
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shuzizhongsheji
有用的数字钟设计文档,有秒表、闹钟等模块,希望对大家有用!(JUST LEARN FROM IT!!ENJOY!)
- 2013-07-18 11:02:24下载
- 积分:1
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myuart
使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分:1
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Some_classic_examples_of_VHDL_language_source_code
VHDL语言的一些经典实例源代码,包括状态机,时序电路,组合逻辑电路等(Some classic examples of VHDL language source code, including the state machine, sequential circuits, combinational logic circuits)
- 2010-07-11 12:50:06下载
- 积分:1
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RGMII测试程序
RGMII测试程序,在板子测试验证过,可以使用,初学者可以参考下
- 2022-03-19 00:31:59下载
- 积分:1
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基于dds的波形发生器
说明: DDS的基本原理主要由五部分组成,分别是;相位累加器,正弦波形存储器,数模转换器,低通滤波器和时钟,将相位累加器输出的数据作为地址,用来查询表的数据,将取出的正弦数据通过数模转换器输出模拟信号,模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)
- 2020-09-16 23:34:30下载
- 积分:1
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FPGA
FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)
- 2016-07-13 08:53:07下载
- 积分:1
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tcd_driver
东芝ccd产品tcd1209驱动程序,生成1209所需的驱动波形(toshiba ccd tcd1209 )
- 2021-02-23 09:29:40下载
- 积分:1
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xapp460
说明: 利用FPGA实现TMDS接口标准,可用于DVI以及HDMI接口的FPGA实现(含文档)(Video Connectivity Using TMDS I/O in
Spartan-3A FPGAs)
- 2021-04-13 11:48:56下载
- 积分:1
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数字钟,带调时加闪烁
24小时计时,可调时间,调时时闪烁,同时输入调时信号去抖
- 2022-01-26 20:17:57下载
- 积分:1