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FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分：1
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本例为电子琴VHDL程序原代码,电子琴,可实现基本功能
本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of
- 2022-03-23 15:59:38下载
- 积分：1
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基于VHDL+FPGA的DDS信号发生设计，已经通过调式
基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
- 2022-06-28 11:38:23下载
- 积分：1
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Flash
说明： FPGA Verilog控制FLASH片外读写(Verilog Controls FLASH Out-of-Chip Read-Write)
- 2020-06-22 21:40:01下载
- 积分：1
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JOP kernel, which is the core of the core, the Chinese can not find basic inform...
JOP的内核文件，这是核心的核心，中文资料基本找不到-JOP kernel, which is the core of the core, the Chinese can not find basic information
- 2022-07-20 02:09:37下载
- 积分：1
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E1（一级欧洲传输标准）
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)
- 2023-08-26 23:00:03下载
- 积分：1
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EEPROM_at25320a
Commponent for drivering EEPROM memory AT25320 from Avalon bus.
- 2013-11-22 00:04:04下载
- 积分：1
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用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS
用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
- 2022-07-22 06:50:26下载
- 积分：1
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xiaomi
新版 小米抢购器 -源码
已经测试，代码很有用，已经抢了好几个小米3了，希望对大家有用(The new millet to snap up- source
Have test, the code is useful, has robbed several millet 3, hope useful for everyone)
- 2014-01-08 18:26:40下载
- 积分：1
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Input from the MIC for some audio and then AOUT interface from broadcast in the...
从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code
- 2023-06-09 21:15:03下载
- 积分：1
