登录
首页 » VHDL » 4x4 electronic locks central control system. Six input control.

4x4 electronic locks central control system. Six input control.

于 2022-02-10 发布 文件大小:139.38 kB
0 48
下载积分: 2 下载次数: 1

代码说明:

4X4电子密码锁的中央控制系统。控制6位输入。-4x4 electronic locks central control system. Six input control.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • liushui
    本程序实现流水线功能,您可根据自己需要更改参数,试用芯片xilinx,用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)
    2016-03-07 09:26:28下载
    积分:1
  • EDA
    说明:  十进制到十六进制转换的程序。程序要求从键盘取得一个十进制数,然后把该数以十六进制的形式在屏幕上显示出来。(Decimal to hex conversion program. Procedural requirements to obtain a decimal number from the keyboard, and then the hexadecimal number to be displayed on the screen.)
    2011-03-27 16:42:04下载
    积分:1
  • taxivalue
    我用FPGA来实现,这是一个出租车计价器,用来计算里程,我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)
    2020-07-12 19:08:52下载
    积分:1
  • 这个免费的CPU
    This free cpu-ip! use verilog
    2023-07-21 16:20:04下载
    积分:1
  • TOFED_Dataflow
    Take its complement by applying DeMorgan’s theorem to obtain F in the form of product of complemented products.
    2014-11-08 06:56:35下载
    积分:1
  • ethernet_loopback
    通过FPGA驱动千兆以太网口,完成SPARTAN6上的UDP数据包闭环测试,即通过网口发送数据包到FPGA,FPGA内部将接收到的数据返回到PC机,建议测试之前添加ARP静态绑定,FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到,发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
    2017-11-20 10:21:38下载
    积分:1
  • PIP
    基于FPGA的画中画处理PDF技术文档,采用SD卡里图片读出来做为底图,然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation )
    2014-07-10 17:56:04下载
    积分:1
  • Desktop
    说明:  qpsk的fpga实现,包含调制和解调部分,使用verilog语言(FPGA implementation of QPSK)
    2019-03-16 02:52:26下载
    积分:1
  • VHDL 编写的RAM例子
    VHDL 编写的RAM例子-RAM prepared VHDL example
    2023-03-23 05:20:03下载
    积分:1
  • VerilogHDL
    本书简要介绍了Verilog硬件描述语言的基础知识,包括语言的基本内容和基本结构 ,以及利用该语言在各种层次上对数字系统的建模方法。书中列举了大量实例,帮助读者掌握语言本身和建模方法,对实际数字系统设计也很有帮助。本书是Verilog HDL的初级读本,适用于作为计算机、电子、电气及自控等专业相关课程的教材,也可供有关的科研人员作为参考书。(This book briefly introduces the Verilog hardware description language basics, including basic elements of language and basic structure, and the use of the language at various levels on the digital system modeling. The book lists a large number of examples to help readers master the language itself and the modeling of the actual digital system design is also helpful. Verilog HDL book is a primer for a computer, electronic, electrical and automatic control and other specialized courses related to materials, but also for the researchers as a reference.)
    2010-05-11 19:54:29下载
    积分:1
  • 696518资源总数
  • 104297会员总数
  • 29今日下载