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verilog 写的 多功能数字钟
verilog 写的 多功能数字钟-verilog to write multi-functional digital clock
- 2023-03-18 14:30:04下载
- 积分：1
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verilog.HDL.examples
许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)
- 2020-06-26 04:40:02下载
- 积分：1
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pedometer
本文设计了基于加速度传感器的计步器，并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动，产生脉冲，将脉冲放大后经过施密特触发器整型为方波，并给出了方波的调试电路图。然后编写程序，利用D触发器检测方波的上升沿，当上升沿到来时，计数，并对十位、个位分别编码，然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。(This article is designed pedometer-based acceleration sensor and the corresponding results recorded by simulation and debugging. The experiments by first acceleration sensor detects the movement of the target object, generates a pulse, the pulse amplification is a square wave after the Schmitt trigger integer, and gives the the debug circuit diagram of a square wave. Then write procedures, the use of the rising edge of the detection of the square wave of the D flip-flop, when the rising edge, the count, and ten bits are encoded, and then alternately by the enable signal output of the digital control. In this paper, a simulation and debugging procedures, results.)
- 2013-03-13 08:58:22下载
- 积分：1
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electricwatch
用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能(VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions)
- 2010-05-07 17:11:53下载
- 积分：1
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OFDM_FPGA
采用FPGA 来实现一个基于OFDM 技术
的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制
器包括：信道编码（Reed-Solomon 编码），交织，星座映射，FFT 和插
入循环前缀等模块。(FPGA to implement a baseband data based on OFDM technology in the communication system processing section, namely modem. Transmitter modulator includes: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and insert the cyclic prefix modules.)
- 2012-05-22 14:28:42下载
- 积分：1
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fre
本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)
- 2015-08-12 08:39:32下载
- 积分：1
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VHDL-Handbook.pdf
VHDL Handbook by HARDI Electronics AB
- 2015-02-17 17:50:32下载
- 积分：1
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verilog实现的“六进制约翰逊计数器”。
verilog实现的“六进制约翰逊计数器”。-verilog implementation of the " six hexadecimal Johnson counters."
- 2022-05-10 11:02:11下载
- 积分：1
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aiqingmaimai
数字钟蜂鸣器音乐——爱情买卖，很时尚的闹钟音乐代码，经测试，很有感觉。(Digital clock buzzer music- love trading, very stylish alarm clock music code, tested, great feeling.)
- 2020-12-28 01:19:01下载
- 积分：1
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fifo
一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)
- 2011-08-28 10:39:31下载
- 积分：1
