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ddsProm
dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~(dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~)
- 2013-06-13 10:07:16下载
- 积分：1
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Bayer2RGB
Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
- 2020-12-14 15:29:15下载
- 积分：1
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wishbone 源代码，opencore
wishbone 源代码，opencore-wishbone source code, opencore
- 2022-05-13 00:28:04下载
- 积分：1
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一个异步FIFO的verilog实现论文
一个异步FIFO的verilog实现论文-err
- 2022-01-28 06:08:18下载
- 积分：1
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raylrnb (3)
说明： 本资源有一个matlab程序段，是仿真BPSK分别在高斯噪声和瑞利衰落下的误码率，产生图形对仿真值和理论值进行比较(This resource has a matlab program segment, which is the bit error rate of simulated BPSK under Gaussian noise and Rayleigh fading respectively. The generated graph compares the simulated value with the theoretical value.)
- 2019-10-21 21:16:04下载
- 积分：1
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ADC-Parameter
外部ADC采集数据，存为数组文件。通过程序读入，然后即可求出ADC的SNR、SINAD、THD、ENOB等。(External ADC data collection, stored as an array of documents. Read through the program, then the ADC SNR, SINAD, THD, ENOB can be calculated.)
- 2021-03-15 21:39:22下载
- 积分：1
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ssi_tx
VHDL同步串口发送部分，基于Xilinx ISE的编程平台(synchronous serial port sending part on VHDL)
- 2021-01-18 20:08:43下载
- 积分：1
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Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
Qutuas II v7.1的key_gen 对sp1无效
这就是个v7.1 sp1的key_gen
-Key_gen the Qutuas II v7.1 for sp1 invalid This is the v7.1 sp1 months key_gen
- 2023-07-28 18:25:02下载
- 积分：1
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一个8位CISC结构的精简CPU，2还提供了编译器
一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
- 2022-02-28 11:37:41下载
- 积分：1
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M25P80 serial memory for applications Verilog program
针对串行存储器M25P80应用的verilog程序-M25P80 serial memory for applications Verilog program
- 2022-03-12 06:10:14下载
- 积分：1
