登录
首页 » VHDL » UART receiver and transmitter using vhdl

UART receiver and transmitter using vhdl

于 2022-02-06 发布 文件大小:265.10 kB
0 48
下载积分: 2 下载次数: 1

代码说明:

这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出,在接收端进行串行输入和并行输出的算法。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • RISC-V-Reader-Chinese-v2p1
    说明:  RISC-V 芯片设计规范,很有参考价值,开源芯片设计必备参考资料,希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
    2020-07-01 23:00:02下载
    积分:1
  • cordic
    基于VHDL语言编写,可下载到FPGA板子上实现的cordic算法实现的设计,并用该算法实现sin和cos的计算,计算结果显示在数码显示管上,已包含按键防抖动功能的实现。(Based on VHDL language, can be downloaded to the the cordic algorithm implemented in the FPGA board to achieve the design and calculation of sin and cos using this algorithm, the results displayed on the digital display tube is included on the function of the realization of the button shake.)
    2013-03-21 16:52:41下载
    积分:1
  • src
    说明:  假设每个从设备中有可访问APB寄存器16个,位宽均为32比特,16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移2位(byte 偏移)(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
    2020-12-15 13:49:14下载
    积分:1
  • USB 1.1 PHY的代码,verilog语言 USB 1.1 PHY的代码,verilog语言
    USB 1.1 PHY的代码,verilog语言 USB 1.1 PHY的代码,verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
    2022-01-25 23:39:51下载
    积分:1
  • VHDL implement serial port, it can communicate with pc, it can accept and send m...
    用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
    2022-02-11 22:49:32下载
    积分:1
  • Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法...
    Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
    2023-06-15 23:20:03下载
    积分:1
  • 用于sopc builder添加组件用的ps/2 键盘 ipcore
    用于sopc builder添加组件用的ps/2 键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore
    2022-03-12 14:54:04下载
    积分:1
  • iq_balance
    调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
    2021-04-23 17:48:47下载
    积分:1
  • AD4003_CTR
    一个AD4003的测试/控制程序,2Ms/s,18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)
    2020-08-24 08:18:16下载
    积分:1
  • CPLD_DEMO_OK
    可以给VHDL初学者看的实例,全部经过验证(VHDL beginners can see examples of all the proven)
    2011-01-12 21:09:45下载
    积分:1
  • 696518资源总数
  • 104297会员总数
  • 29今日下载