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In this case is a convolutional code on a simple algorithm, using verilog HDL la...

于 2022-02-05 发布文件大小:102.06 kB

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本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.

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一些有用的PicoBlaze的来源。
Some useful PicoBlaze sources.

2022-01-26 02:08:20下载

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verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9...
verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10

2022-08-15 23:59:39下载

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WA
说明： QUARTUS2 16.9 VHDL FPGA ENDAT2.2

2020-11-24 17:50:21下载

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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

2013-07-25 14:43:43下载

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this come from alter ,you can look and find it on line.
this come from alter ,you can look and find it on line.

2022-12-12 10:20:03下载

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基于vhdl的PWM发生器
基于vhdl的PWM发生器-VHDL-based PWM generator

2022-03-04 15:27:12下载

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nco11000
实现输入一正弦波和噪声的叠加，介绍详细欢迎下载(The input of a superposition of sine wave and noise introduced in detail)

2010-05-16 14:19:53下载

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16x2液晶显示驱动设计的FPGA。
16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

2022-02-27 02:16:22下载

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Verilog_golden
说明：很好的免费学些 verilog教程欢迎下载(Learn a good free download verilog tutorials welcome)

2009-08-02 14:45:56下载

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jishuqi
计数器是数字系统中使用最多的时序电路，它不仅能用于对时钟脉冲计数，还可以用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。(Counter is the most frequently used sequential circuit in digital system. It can be used not only for counting clock pulses, but also for frequency division, timing, generating beat pulses and pulse sequences, and performing digital operations.)

2018-11-26 15:42:03下载

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In this case is a convolutional code on a simple algorithm, using verilog HDL la...

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