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uart-for-fpga
Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分:1
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开关、 灯、 和多路复用器-DE2-115
此练习的目的是要了解如何连接简单的输入和输出到 FPGA 芯片的设备和
实现电路,使用这些设备。我们将作为投入 DE2 系列主板上使用 SW17
- 2023-03-02 02:20:04下载
- 积分:1
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verilog_lab_solution
Verilog 实验代码。。。经典的,里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)
- 2011-12-01 23:44:40下载
- 积分:1
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希尔伯特变换是通信系统中的一个重要组成部分,如:
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.
The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940).
The design is fully pipelined for maximum throughput.
- 2023-02-02 09:20:04下载
- 积分:1
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Several common multiplier Verilog, VHDL code
几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
- 2022-03-12 09:47:07下载
- 积分:1
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asynchronous serial communication port of the FPGA, function (1) serial data rec...
异步串口通信口在FPGA实现,功能有(1)串行数据接收的同步控制;(2) 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
- 2023-06-21 16:25:03下载
- 积分:1
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lcd
vhdl code fpga for lcd 2*16
- 2017-09-22 23:15:51下载
- 积分:1
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扰码器Verilog
实现扰码的功能,主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)
- 2020-10-17 17:27:27下载
- 积分:1
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VHDL achieve a frequency measurement of dollars, development environment for any...
一个vhdl实现的测频计,开发环境为任何支持vhdl语言的厂商提供的开发环境
-VHDL achieve a frequency measurement of dollars, development environment for any VHDL language support for manufacturers of the development environment
- 2022-01-28 17:39:53下载
- 积分:1
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timescale-1ns
说明: 这是一款由晶振产生的脉冲控制的数字钟,可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)
- 2011-04-13 19:21:39下载
- 积分:1