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NAND FLASH控制器
NAND FLASH的控制器,Micro的样例,MCU端口有用到wishbone总线(软硬Core均可以)
- 2023-01-25 13:45:04下载
- 积分:1
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resolutionquartusII
用verilog编写的分辨率提高的源代码 采用双线性插值(Written resolution with the verilog source code to improve the use of bilinear interpolation)
- 2021-05-14 18:30:02下载
- 积分:1
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median
说明: 用verilog编辑的中值滤波器!语言旁表有注释方便理解!(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分:1
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Altera-FPGA_CPLD-design-Advanced
《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性,LogicLock设计,时序约束,设计优化,高级工具及系统级设计技术,是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)
- 2017-03-08 19:47:32下载
- 积分:1
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ch3ex
部分组合逻辑数字电路的VHDL代码,包含必要的功能描述(Some combinational logic digital circuits VHDL code, containing the necessary functional description)
- 2009-01-31 21:26:34下载
- 积分:1
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简单的32位RISC CPU内核
我是在韩国仁荷大学学生。这是项目结果的计算机体系结构。它的 CPU 核心,32 位 RISC 系统。它可以在 300 MIPS opreated。1cycle / 1instruction 系统。它提出简单的哈佛架构。和做简单的算术逻辑。
- 2022-01-28 09:03:42下载
- 积分:1
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sinwave
使用verilog hdl语言编程正弦波信号,能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results
)
- 2013-09-18 15:27:27下载
- 积分:1
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suzimiaobiao
数字秒表的实现,我还写个具体的过程要求等,(there is function of clock,it very useful)
- 2011-09-20 14:28:30下载
- 积分:1
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静态时序分析
说明: fpga 静态时序分析 是电子工程中,对数字电路的时序进行计算、预计的工作流程,该流程不需要通过输入激励的方式进行仿真。(Static time series analysis is a work flow which can calculate and predict the time series of digital circuits in electronic engineering.)
- 2020-06-16 11:10:56下载
- 积分:1
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freq
vhdl八位十进制数字频率计的设计,顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分:1