-
PWM
说明: 通过一个计数器来实现输出信号的占空比要求,可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
- 2020-06-16 13:20:02下载
- 积分:1
-
WCDMA_DPD
WCDMA数字直放站中数字预失真研究及其FPGA实现(WCDMA Digital Repeater digital pre-distortion and its FPGA implementation)
- 2011-10-16 19:24:50下载
- 积分:1
-
32位D触发器
D触发器是最简单,最常用,最具代表性的时序元件,它是现代数字系统设计中最基本的底层时序单元,甚至是ASIC设计的标准单元。JK和T触发器都由D触发器构建而来。D触发器的描述包含了Verilog对时序电路的最基本和典型的表达方式,同时也包含了Verilog许多最具特色的语言现象。
- 2022-08-17 11:15:02下载
- 积分:1
-
8B_10BENCODER
基于8B10B的编解码模块的设计,使用verilog HDL语言,具有实用价值。(8B10B encoder)
- 2014-05-23 16:39:25下载
- 积分:1
-
electrical lock
一个用Verilog写的电子锁工程,带testbench。(An electronic lock project written in Verilog with testbench.)
- 2020-06-30 05:00:01下载
- 积分:1
-
FPGA锁相环实验
说明: FPGA锁相环实验:
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分:1
-
at7_ex04
通过LED闪烁控制器的代码,使用Vivado工具配置定义一个IP核,在用户工程中可随意添加这个IP核作为设计的一部分,如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
- 2018-04-09 18:41:52下载
- 积分:1
-
基于FPGA的数字时钟设计
基于FPGA的数字时钟设计,通过lcd1602显示时钟,时钟可调节,主要针对学习用FPGA来驱动lcd1602显示,以及学习verilog硬件描述语言。
- 2022-02-12 03:20:21下载
- 积分:1
-
ds1820
基于FPGA的温度控制系统 VHDL 数码管显示温度 ds1820 温度报警(The temperature control system based on FPGA VHDL digital display temperature ds1820 temperature alarm)
- 2015-01-06 14:08:43下载
- 积分:1
-
Timing_Closure
详细讲解时序约束培训教材,有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)
- 2010-08-12 20:02:33下载
- 积分:1