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VerilogDHL
VerilogHDL教程,很详细全面的Verilog教程,循序渐进,由浅入深,十分好的学习资料(VerilogHDL tutorial, very detailed and comprehensive Verilog tutorial, step by step, progressive approach, a very good learning materials)
- 2011-07-13 14:19:53下载
- 积分:1
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基于AMBA总线的ahb_sram_slave设计资源
基于AMBA总线的sram slave设计,32位总线,支持8/16/32位数据读写,SRAM空间大小是64KB,单周期读写(本设计不支持wait,即hready都拉高)
SRAM是一个单端口(FiFo是双端口,这里就是一边读写就行,就使用单端口),大小是8*8K,支持低功耗(工作状态的功耗是low power standby 状态的几百倍),支持BIST
也预留了DFT port端口,可以有三种Model:function,BIST,DFT
- 2022-08-25 18:20:49下载
- 积分:1
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HDB3
HDB3 encoder and decoder(HDB3 decoer)
- 2020-11-11 12:29:45下载
- 积分:1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码,能够实现时分秒的计时,可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分:1
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RX_RS_DEC
OFDM系统新型RS编解码的verilogHDL设计,经测试误码率性能提高(OFDM system verilogHDL new RS codec design, improved bit error rate performance tested)
- 2020-12-31 10:59:00下载
- 积分:1
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demo
NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)
- 2013-07-19 11:17:29下载
- 积分:1
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prj_ex_5
自动化仿真平台的搭建使用代码,经过具体的仿真和优化,发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)
- 2017-09-21 15:11:33下载
- 积分:1
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ALU verilog
设计与实现的 ALU RISC 处理器。
- 2022-05-05 15:25:09下载
- 积分:1
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cnt60
de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)
- 2011-11-28 20:28:12下载
- 积分:1
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vivado-constraints
vivado软件中的时序约束参考资料,很详细,不同的约束种类对应不同的命令。(vivado-using-constraints)
- 2019-05-15 16:20:58下载
- 积分:1