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是使用VHDL语言编写的基于FPGA的uart的源代码!
是使用VHDL语言编写的基于FPGA的uart的源代码!-VHDL language is to use FPGA-based uart source code!
- 2022-07-10 13:34:40下载
- 积分:1
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RecentProjectCleaner
vs自定义插件开发,带卸载功能,经测试完全可用,分享给大家,可以学习!(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)
- 2014-12-24 11:35:54下载
- 积分:1
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使用VHDL实现三角函数的计算
为了便于计算结果在FPGA中后续的计算和ip核中的调用,本代码输入信号为普通浮点型数据,输出为32位表示的浮点型数据。
- 2022-07-21 05:59:31下载
- 积分:1
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VHDL
软件式的VHDL学习工具,能帮助你更好的掌握VHDL的应用-VHDL-based software, learning tools, can help you better grasp the application of VHDL
- 2022-07-01 16:13:22下载
- 积分:1
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code
modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)
- 2009-07-17 10:26:46下载
- 积分:1
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tr_wave
FPGA编写的三角波发生器,可以产生100HZ~500KHZ以上的三角波,波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)
- 2007-08-25 03:15:38下载
- 积分:1
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Motion_control
基于FPGA的运动控制系统设计,包含位置、速度控制等(motion control)
- 2020-11-29 13:09:28下载
- 积分:1
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非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作
非常优秀的国外VHDL设计教程,可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
- 2023-05-15 08:55:03下载
- 积分:1
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baseband_verilog
verilog实现的基带信号编码,整个系统分为六个模块,分别为:时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分:1
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mooor状态机的VHDL程序,代码,状态机,关键是分析各个状态之间的切换...
mooor状态机的VHDL程序,代码,状态机,关键是分析各个状态之间的切换-mooor zhuangtaiji zhuagtaiji guanjianshi gege zhuangtai zhijian de qiehuan
- 2022-02-06 05:30:36下载
- 积分:1