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基本的 VHDL 程序
基本的VHDL程序本rar文件。 请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2022-05-24 21:08:13下载
- 积分:1
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ldpc-for-fpga-decoding
ldpc译码算法的matlab实现,码长960,码率1/2,完全模拟fpga硬件实现语言,量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)
- 2021-04-12 21:38:56下载
- 积分:1
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AV视频信号输入后,存入SDRAM中然后在PC上面进行显示的代码。...
AV视频信号输入后,存入SDRAM中然后在PC上面进行显示的代码。-AV video signal input into the SDRAM in the PC and then display the code above.
- 2023-03-27 03:30:03下载
- 积分:1
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CY7C63723
CY7C63723 功能及其引脚描述,外围电路和仿真数据(The CY7C637 is an 8-bit RISC OTP microcontroller.)
- 2009-07-13 14:30:05下载
- 积分:1
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SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。...
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。-This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
- 2023-07-19 13:10:03下载
- 积分:1
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ug848-VC707-getting-started-guide
vc707 board getting started guide
- 2018-06-14 05:52:39下载
- 积分:1
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ComChange-12061629
说明: 并行读写14路串口数据,数据被写入FIFO,在收到读写信号后,SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分:1
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FP6182
说明: PF6182是一款很好的DC-DC同步降压IC。输出电压可调整,电流达2A。非常好用(PF6182 is a good DC-DC synchronous buck IC. Adjustable output voltage and current up to 2A. Very easy to use)
- 2011-03-16 10:26:05下载
- 积分:1
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EMAC6
verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)
- 2013-01-09 00:04:20下载
- 积分:1
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lab4_0419
Run-Length Encoder
Example:
Input Sequence (hexadecimal format): 0A, 14, 14, 14, 14, 14, 14, 14, 56, 56, 56, 56, 56, 32, 32, 07
Output Sequence (hexadecimal format): 0A, 14, 87, 56, 85, 32, 32, 07
- 2015-05-04 05:36:31下载
- 积分:1