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ahb_verilog_design
代码为ahb interface ,用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)
- 2020-12-21 14:49:07下载
- 积分:1
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DE2_Default
基于DE2开发板的VGA显示模块,仅供大家参考(DE2 development board based on the VGA display module, for your reference)
- 2008-07-21 16:12:32下载
- 积分:1
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Verilog实现基于FPGA的反应测试系统
2016年4月19日22:51:52
反应测试系统
- 2022-01-27 17:49:48下载
- 积分:1
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fpga_2014_flappy_bird
用VHDL语言写了个FLAPPY_BIRD的程序,利用板子与屏幕可以运行游戏(VHDL language to write a program FLAPPY_BIRD by the board and the screen can run the game)
- 2020-11-06 09:59:49下载
- 积分:1
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ADV7513 HDMI条形显示,支持1920*1080,最高收入时钟165MHz,完整的Verilog语言实现,并且有完整的IIC驱动代码
- 2022-02-24 11:32:13下载
- 积分:1
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BCD-counter
一个2位的BCD码十进制加法计数器电路,输入为时钟信号CLK,进位
输入信号CIN,每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT,输入时钟信号CLK用固定时钟,进位输入信号CIN.
(A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)
- 2020-10-28 19:29:58下载
- 积分:1
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Signal
基于FPGA的DDS相位累加器,连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)
- 2018-05-10 15:19:05下载
- 积分:1
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ahb_sramc_vtb
ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)
- 2020-08-25 20:48:15下载
- 积分:1
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Encode5b_4b
PD里面的4B5B编码,欢迎使用~~~~~~~~~~~~~~~~~(4B5B code in PD3.0 or USB3.0, welcome to use~~~~~~~~~~~~~~)
- 2020-12-03 09:09:25下载
- 积分:1
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VHDL
用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分:1