-
VHDL实用教程(潘松),非常经典讲解VHDL语言,包含基本语法及实例。...
VHDL实用教程(潘松),非常经典讲解VHDL语言,包含基本语法及实例。-VHDL Practical Guide (Pan Song), is a classic on the VHDL language, including basic grammar and examples.
- 2022-08-07 10:44:16下载
- 积分:1
-
基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码,其功能主要有:时间设置,时间显示,跑表,分频,日期设置,日期显示等...
基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码,其功能主要有:时间设置,时间显示,跑表,分频,日期设置,日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
- 2022-02-12 09:36:35下载
- 积分:1
-
altera公司cpld的原理图库(protel格式)
altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.
- 2022-03-18 02:53:20下载
- 积分:1
-
vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验...
vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验-Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
- 2022-12-25 18:00:03下载
- 积分:1
-
jk-filpflop
这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)
- 2013-11-19 11:43:07下载
- 积分:1
-
1
verilog 典型电路设计包含各种常用电路的源码和详细的解释,适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use
)
- 2014-03-19 10:48:41下载
- 积分:1
-
基于fpga的正弦波发生器设计,有一定的参考价值,写的比较详细...
基于fpga的正弦波发生器设计,有一定的参考价值,写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
- 2022-12-22 09:40:03下载
- 积分:1
-
chuankou_huihuan
说明: FPGA与PC端实现串口数据的收发,先从PC端接收数据,然后发回给电脑,可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)
- 2020-06-16 10:20:01下载
- 积分:1
-
FDPIM_Encode
关于语音通信信道调制的程序代码,是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)
- 2013-12-11 09:27:39下载
- 积分:1
-
全加器的VHDL程序实现及仿真
全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
- 2022-02-03 16:51:49下载
- 积分:1