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SASX
说明: Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
- 2020-06-24 11:40:02下载
- 积分:1
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bcd_to_dec
VHDL code for converting BCD to Decimal
- 2018-02-13 09:45:16下载
- 积分:1
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123
说明: 系统介绍了数字开发系统平台FPGA设计中的部分技巧 对于FPGA开发研究人员具有一定的指导和帮助意义(Systematic introduction of digital development platform FPGA design techniques for FPGA development of some of the researchers have some sense of guidance and help)
- 2011-03-24 10:34:07下载
- 积分:1
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project_comfinal
说明: it can add two numbers and shows the answer
- 2019-05-28 19:16:02下载
- 积分:1
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DE2-115 nios 核网络测试
在DE2-115板上,移植simple socket server,实现PC 上使用Telnet客户端 通过网口控制开发板上的LED灯,亲测可用。
- 2022-03-18 08:48:04下载
- 积分:1
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zobrazenie_16_bit_cisla_paralel
16 bit switch input view in hexa format on 7seg display
- 2013-08-16 00:50:49下载
- 积分:1
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qiartus2use
verilog仿真硬件的工具qiartus2的使用教程,内容简单易懂,初学必备(Verilog simulation tool for hardware qiartus2 the use of tutorials, easy-to-read content, learning essential)
- 2008-06-19 08:03:04下载
- 积分:1
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52_divider
多倍(次)分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_stim.vhd
(Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)
- 2009-09-04 09:52:18下载
- 积分:1
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xilinx-FPGA
xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)
- 2012-08-10 13:07:41下载
- 积分:1
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LDPC最小和算法校验节点更新单元CNU verilog设计
16输入校验节点更新单元,实现分离、分类、比较,最终输出与端口对应的最小值(即除去自身以外的最小值)。内附仿真结果图,供大家理解。
- 2023-05-07 13:10:03下载
- 积分:1