用verilog实现msk信号调制器.zip
【实例简介】msk调制顶层模块msk_top.v
module msk_top(clk_100MHz, clk_2MHz, clk_1MHz, reset,x,msk_out);
input clk_100MHz;
input clk_2MHz;
input clk_1MHz;
input reset;
input x;
output [32:0] msk_out;
wire b_i, b_q;
wire [15:0] sine, cosine;
//调用亟待数据处理模块
S2p s2p(
.clk(clk_2MHz), clk_div2(clk_1MHz),reset(reset),
.x(x),.b_i(b_i),.b_q(b_q));
//调用I,Q路加权模块iqsin.v
Iqsin iqsin(
.clk(clk_100MHz),. reset(reset), .b_i(b_i),.b_q(b_q),
.SINE(sine),COSINE(cosine));
//载波调制相加模块 iqmodu.v
Iqmodu iqmodu(
.clk(clk_100MHz), .i_i(cosine),.q_q(sine),.msk_out(msk_out));
endmodule
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