altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
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开关磁阻电机系统理论与控制技术
开关磁阻电机系统理论与控制技术，介绍了基本理论，电机设计，Matlab仿真内容提要本书共分为8章分别阐述了开关磁阻电机及其控制系统发展概况,推导了电机线性、准线性和非线性数学模型,给出了开关磁阻电机计算设计程序,讲述了开关磁阻电机有限元分析方法,研究了开关磁阻电机调速系统的控制策略,详细介绍了利用软件建立开关磁阻电机仿真模型的步骤,井进行了稳态性能仿真和动态性能仿真,最后针对DSP对开关磁阻电机有位置传感器和无位置传感器调速系统进行理论分析与设计开本书适用于从事电力电子及电气传动专业高等学院教师和研究生,以及相关专业好、运的科研机构的研究人员和直流关磁阻木空把矿、航功率范本磁阻电图书在版编目(CIP)数据上的拓机线性开关磁阻电机系统理论与控制技术/吴红星编著.一北京:中国了开关电力出版社,20107略,以(现代工业自动化技术应用丛书)电SBN978-7-5123-0336-2行有限:1.①开…Ⅱ.①吴…Ⅲ.①开关控制-磁阻电机-系统理在Max论②开关控制-磁阻电机控制Ⅳ.①TM352线:对车中国版本图书馆CIP数据核字(2010)第070773号系统仿J结构来》电枝该模型E控制器矩分配巨中国电力出版社出版、发行机的发E北京三里河路6号1004htp/www.cspp.com.cn)磁阻电积北京丰源印剧厂印刷电右各地新华书店经售建立开弓2010年8月第一版2010年8月北京第一次印剧统稳态忙787毫米X1092毫米16开本17印张452千字了优化。印数000-3000册定价36.00元电机调这敬告读者法,推毛木书封面贴有防伪标签,加热后中心图案消失各模型过本书如有印装质量问题,我社发行部负责退换电初版权专有翻印必究关磁阻欠压保折前厂言开关磁阻电机调速系统具有结构简单、坚固、工作可靠、成本低、系統控制灵活、调速性能好、运行效率高、温升低等诸多优点,它综合了交流变频调速系统的坚固耐用、适用于恶劣环境和直流调速系统的可控性好等优良特性,被专家视为电气传动系统发展过程中的一个里程碑。开关磁阻电机特别适用在恶劣环境和要求超高速的场合下运行,并可广泛地应用在纺织、造纸、煤矿、航空、机槭等领域的造纸机、浆纱机、采煤机,风机、水泵、家用电器和机器人等负载上,功率范围从几瓦到儿兆瓦,转速范围从几转到儿万转。本书的宗旨是,着眼于实用技术,并兼顾到发展趋势。考虑到实际应用的需要,介绍了开关磁阻电机的几种结构形式,针对新型开关磁阻电机进行论述,总结开关磁阻电机在绕组结构形式上的拓扑结构,论述各种绕组拓扑结构的优缺点。在开关磁阻电机基本方程式的基础上,推导电机线性数学模型和准线性数学模型,具体分析绕组电流、绕组磁链、绕组电感和电磁转矩,给出了开关磁阻电机设计步骤,并分析了转矩脉动产生的原因,研究开关磁阻电机调速系统的控制策略,以DSP为控制芯片,给出了开关磁阻电机调速系统设计方法和基本设计软件。电机本体设计方面:给出计算程序,对128电机进行各类参数的计算:对开关磁阻电机进行有限元分析:利用 Ansoft软件建立开关磁阻电机的有限元模,用 RMxprt得到二维几何模型,在 Maxwell2D的瞬态求模块下进行有限元分析;分析得到的绕组电流、绕组磁链、电磁转矩曲线:对转子极弧系数、轴径、开通角等参数进行优化分析:在分析有限元计算的矩角特性曲线和系统仿真后的转矩输出波形的基础上,得出产生转矩脉动的根本原因,通过改进电机定子磁极的结构来减小气隙磁场的突变,通过修改气隙等参数从而减小和抑制转矩脉动。电机控制策略方面:根据数学模型研究基于永磁磁通控制开关磁阻电机非线性数学模型。在该模型的基础上,研究基于永磁磁通控制开关磁阻电机调速系统的控制策略。设计绕组电流闭环控制器、转速调节控制器,硏究基于永磁磁通控制开关磁阻电机转矩分配的控制策略,推导了转矩分配函数,并设计转矩控制器。分析开关磁阻电机的发电运行机理和能流关系,对开关磁阻电机的发电运行理论进行线性分析,推导基本电路方程和相电流解析式;通过线性模型,分析开关磁阻电机的有效发电条件电机仿真技术方面:用 MATLAB软件建立开关磁阻电机的准非线性动态仿真模型的基础上,建立开关磁阻电机系统的系统模型,并对系统模型进行了稳态性能仿真和动态性能仿真。利用系统稳态性能仿真,综合考虑最大平均转矩和效率这两个优化目标,对升关磁阻电机的开关角进行了优化。针对传统PⅠ控制策略对开关醚阻电机调速系统进行仿真,得到采用传统P控制策略的电机调速系统的电机相电流波形和系统转矩波形。深入研究基于模糊控制的控制理论和控制方法,推导基于模糊控制的搾制算法,提出一种模糊PI相结合的控制方法,并建立仿真模型,对各模型进行比较,以便得到最佳控制策略电机控制系统方面:介绍开关磁阻电机调速特点,分析电机驱动功率电路拓扑结构,介绍开关磁阻电机调速系统转子位置传感器分类及使用方法。设计了驱动电路,过流保护电路、过压和欠压保护电路、电机专用控制电路等硬件。利用T公司的电机专用DsP设计开关磁阻电机有位全书共8章,第1章介绍了开关磁阻电机调速系统的概况、发展趋势及主要应用领域。第2章介绍了开关磁阻电机的线性数学模型、准线性数学模型及非线性数学模型。第3章分析了开关磁阻电机的各类损耗,介绍了开关磁阻电机本体的设计方法。第4章利用 Ansoft软件建立开关磁阻电机的有限元模,用 RMxprt得到二维几何模型,在 Maxwell2D的瞬态模块下进行有限元分析。分析得到的绕组电流、绕组磁链、电磁转矩曲线。对转子极弧系数、轴径、开通角等参数进行优化分析。第5章介绍了开关磁阻电机调速系统在各类调速系统的地位,设计开关磁阻调速控制系统硬件。第6章针对开关磁阻电机调速特性研究开关磁阻电机控制策略和发电机理。第7章用 MATLAB软件建立开关磁阻电机系統的系统模型,并对系统模型进行稳态性能仿真和动态性能仿真。第8章针对DSP对开关磁阻电机有位置传感器和无位置传感器调速系统进行理论分析与设计。前言本书由吴红星编著,各章编写工作有赵晢、嵇恒、刘莹、钱海荣、黄冬林、倪天、郭庆波、第1章叶宇骄等参与。全书由吴红星统稿,寇宝泉教授支持本书的编写并审阅了书稿。编写过程中,参1.1阅和利用了国内外大量文献、资料,在此对原作者一并致谢。1.2限于作者水平,加上时间仓促,缺点、错误在所难免,热忱欢迎广大读者批评指正。1,2,1,2,21,3于14J14.114.214.314.414.514.614.714.81.5开1.6开第2章2.1开22开2.2,122.32,242,2.52.3开24开2,4.124.22.4.324424.5主要应用领域。第2第3章分析了开关soft软件建立开关模块下进行有限元径、开通角等参数最》设计开关磁阻调速略和发电机理。第7态性能仿真和动态速系统进行理论分前言第1章绪论、倪天、郭庆波、11开关磁阻电机的发展概况…编写过程中,参12开关磁阻电机的结构特点…,+…日2…2121开关磁阻电机的优点………者批评指正。1.2.2开关磁阻电机的缺点和和国国面自和“““““国目目围把的和一41.3开关磁阻电机的优化方法141.4开关磁阻电机系统抑制转矩脉动技术…1.4.1基于抑制转矩脉动的传统控制策略…14.2基于抑制转矩脉动的线性化控制…614.3基于抑制转矩脉动的变结构控制61.44基于抑制转矩脉动的智能控制理论…14.5基于抑制转矩脉动的转矩分配策略…………146基于抑制转矩脉动的迭代学习控制…1014.7基于抑制转矩脉动的微步控制策略…………101.4.8其他方法015开关磁阻电机未来研究方向…1.6开关磁阻电机的工业应用………………………2第2章开关磁阻电机的工作原理及数学模型142.1开关磁阻电机基本原理22开关磁阻电机的一些基本结构…1422.1单相开关磁阻电机……………142.22两相开关磁阻电机……………152.2.3三相开关磁阻电机………………52.24四相开关磁阻电机……………………………………1622.5五相以上开关磁阻电机1623开关磁阻电机改进结构…1624开关磁阻电机数学模型……………21224.1电路方程…2.42机械方程2224,3机电联系方程*…,…222.44线性模型……1232,4.5准线性模型25混合励磁开关磁阻电机数学模型…日型道日副上理福2.5混合励磁电机磁路特点………………252混合励磁开关磁阻电机转矩平衡方程……4446i4.4.7孟第3章开关磁阻电机电磁设计……………………3744863.1开关磁阻电机设计及优化方法……………13945有限31.1电机本体结构设计………94.5.R…………393.1.2电机参数优化设计………4.52M32开关磁阻电机损耗分析……45.3有321绕组铜损分析…………42046基于车3.2.2机械损耗分析……404.6.1影3.2.3杂散损耗分析…44.62开…………41324电机铁损分析……………………………………………………414.6.3定33开关磁阻电机参数计算…+45第5章开关331电负荷与磁负荷…51开关磁332主要尺寸4534开关磁阻电机本体设计示例…………475.12电34.1相数,极数和绕组端电压……………5.3电压34.2主要尺寸的选择计计4852开关磁343其他结构尺寸及绕组匝数”5.3开关磁阝48344电流及转矩计算……………………………………5053.1开关34.5绕组设计……………………………………………15053.2开关34.6参数计算533开关51534开关第4章开关磁阻电机性能优化…54开关磁阵41电机电磁场的理论基础………………5454.l标准42有限元法54542其他421有限元法的发展55…555.5迭代学买42.2 Ansoft软件简介……………………………555.1基于423 Ansoft有限元法…55,2迭代424电磁场有限元方法的特点及一般步骤65.6开关磁43 RMxprt软件设计及使用方法………15756.1速度43.1启动软件……………5858562转矩432新建SRM模型563电流4.3.3建模结果……68第6章开关磁434仿真计算61开关磁阳43.5模型导出…1111736.1.1与步44 Maxwell2D软件设计及使用方法…………“环“746.12与反44.1打开工程文件………m…“+t74613与直442模型设置……17614与无44.3材料设置………786.1.5与异444边界及激励源设置806.2功率电子44.6设置仿真参数+,90……34……*34447运动部分设置……………………………………………9544.8仿真运算96+:37…014.5有限元分析结果处理………39451 RMxprt输出的性能曲线………10139452 Maxwell2D的求解结果…394.3有限元后处理………1044046基于转矩波动抑制电机本体优化…1-11054046.1影响转矩波动的因素…404.62开通角、关断角对转矩波动的影响…………………106…41463定子磁极结构对转矩波动的影响……………xx+107414第5章开关磁阻电机的控制策略…5.开关磁阻电机控制方式……,中日副日是…:1045…:4551l角度位置控制(APC)1111045512电流斩波控制(CCC)……………………………1l475.1.3电压斩波控制(CVC)……………4852开关磁阻电机调速特性53开关磁阻电机能量回馈控制…::1:1111248…4853.1开关磁阻电机发电运行机理…50532开关磁阻电机发电运行的励磁过程:50533开关磁阻电机的能量变换理论……………………………1451534开关磁阻电机发电状态工作特点……………”…11654开关磁阻电机PD控制::18*54541标准数字PID算法………………19:54542其他PD方法1120……5555迭代学习控制…121:5551基于模型控制系统和迭代学习控制系统概述…………:121555.52迭代学习控制过程和开环PD迭代学习控制……122“565.6开关磁阻电机的转矩分配控制系统设计…123……*5756.!速度调节器设计……………123585.6.2转矩分配函数的设计………425+58563电流控制器设计……………1265968第6章开关磁阻电机调速系统硬件设计……………128696,1开关磁阻电机调速系统在电机控制中的地位1128…736.L.1与步进电动机驱动系统的比较+++:128…746.1.2与反应式同步电动机的比较…………28746.1.3与直流电动机的比较“…自129a776.14与无换向器直流电动机的比较:1297861.5与异步电动机变频调速系统的比较………1298062功率电子器件…………………130622功率GBT工作特点……1317463PWM控制技术…11137.4.6.3.1传统PWM技术…计计……1347.463.2优化后的PWM技术“国计1347.4633空间电压矢量PWM控制…计………13574.6.34跟踪型PWM控制技术1357464开关磁阻电机控制器功率拓扑结构………-13674641不对称半桥主回路…137第8章642H桥主回路…积+…137643不对称半桥改进型”…1378.2644(n+1)型功率变换器1388264.5电容裂相型…“……1388,264.6电容转储型…+1…:1388365整流及吸收回路设计………1398.36.5.1功率吸收电路设计…………………139836.52吸收电路参数计算…::+140846.53整流电路设计……846.54电流采样与处理电路…道上中中和国和8,46.5.5转子位置信号采集与处理……………………1428.5656系统保护电路设计:1498.66.6功率及驱动电路11518.66.61SKH24驱动模块在SRD系统中的应用…………518.6.62S19976DY—桥式驱动器的原理及应用11528.76.63EXB841工作原理…578.8664FCAS50SN60开关磁阻电机功率模块…………1598.第7章基于DSP开关磁阻电机控制器设计……1658.7.DSP的特点1657.2电动机DSP控制系统基础……………………167参考文721DSP电机控制特点…1677.22数字滤波DSP实现方法…………16873有位置传感器DSP控制++117173.1开关磁阻电机控制机理……“已,171732DSP控制开关磁阻电机硬件设计…………………………17733软件设计x+2:::175734电流控制………………………17773.5位置控制178736速度控制……国+…“……“…“…面,,正重自7.3.7换相控制………………181738速度控制器……………x1837.3.9DSP编程示例………………………8474开关磁阻电机无传感器DSP控制…………………:21674.1调速系统硬件描述………………216…133742无传感器开关磁阻电机驱动系统的控制软件…………216…:134743无传感器换相和速度更新算法………………………………218134744速度环:21135745电流控制回路……213574.6斜坡控制器……136747无传感器开关磁阻电机驱动系统的校准………………2313第8章开关磁阻电机调速系统仿真……22813781引言+*13782基于 MATLAB/Simulink的系统建模与仿真分析……128138821仿真软件 MATLAB/Simulink简介…x:12813882,2电机模型的建立……………………23…13883控制系统P控制策略建模与仿真……23013983.1SRM调速系统的无P控制仿真………30…13983.2电机调速系统的PI控制仿真分析……………31…,……,:14084基于模糊控制器的系统仿真分析……………236…:148.4.1模糊控制器的设计1236142842SRM调速系统的模糊控制仿真及结果分析…………………23814285sRM调速系统模糊P控制仿真……………………242………1498.6开关磁阻电机能量回馈建模与仿真…………24351…………151861发电状态的基本电路方程…86.2发电运行的相电流解析…24315287开关磁阻电机控制系统模型分析……2455788开关磁阻电机发电系统模型的建立….…:2521598.81电流滞环控制模块………………………254,+1658.82电流计算模块………2541658.8.3转矩计算模块…254167参考文献……::::::1256…………16716817117117317577178179181中“183184216
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