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fft1024 verilog代码
fft1024 verilog 代码 可以编译成功 建议下载学习(The fft1024 verilog code can compile successful Suggestions for download learning)
- 2017-07-20 10:31:05下载
- 积分：1
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filter
说明： 300Hz带阻滤波，用matlab中fdatool设计参数，然后用labview开发(300Hz bandstop filter, IIR. Firstly, the coefficients are calculated by Fdatool design tool in matlab, and then developed by labview.)
- 2020-06-24 17:40:02下载
- 积分：1
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chaoshengbo_diatance_hc_sr_04
说明： 实现Verilog编程，实现超声波测距模块实现测距功能，并将测得的距离显示在数码管上(Verilog programming is realized, ultrasonic ranging module is realized, and the measured distance is displayed on the digital tube)
- 2020-06-17 16:40:02下载
- 积分：1
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fingerprintjs-master
利用canvas指纹识别，生成浏览器唯一标示。(Using canvas fingerprint identification to generate browser unique mark.)
- 2017-10-13 15:44:06下载
- 积分：1
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SW297850
NFC library for CL reader
- 2020-06-25 16:00:02下载
- 积分：1
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捕获器
身体还是突然就合适就很少听人家说今天人竟然同时(wjtjherjttklgukrfykt)
- 2020-06-19 17:00:01下载
- 积分：1
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Dongle Driver
Dongle Driver for usb for windows seven
- 2018-11-01 20:37:52下载
- 积分：1
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源代码及class文件
说明： 游戏的过程应该是一部分棋子“主动”去翻转，另一部分可以通过其周围的棋子来“被动”翻转。而每一个棋子的状态逻辑值根据引言可知只有翻转和不翻转两种状态(不必考虑多次翻转的情况)，因此可以用0和1来表示。一次翻转操作相当于五个相关单元的逻辑值取反。(The process of the game should be one part of the chess pieces "active" to flip, and the other part can be "passive" to flip through the chess pieces around them. According to the introduction, the logical value of the state of each chess piece can be expressed as 0 and 1, because there are only two states: flip and non-flip (without considering the situation of multiple flips). A flip operation is equivalent to the logical value reversal of five related units.)
- 2020-06-17 17:00:02下载
- 积分：1
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STM32-clock
基于STM32实现电子时钟的设计，可以通过按键、或者串口来进行时间设置(STM32-based electronic clock design, can be key, or serial port to set the time)
- 2020-07-03 22:00:01下载
- 积分：1
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muiti_band
说明： IDL批量实现影像多单波段合成LayerStacking，并进行滤波SavitzkyGolayFilter，然后再拆分为单波段(IDL batch realizes image multi-single band synthesis LayerStacking, filters SavitzkyGolayFilter, and then splits into single bands)
- 2020-12-14 21:49:14下载
- 积分：1
