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imply logic
由忆阻器机制设计蕴含逻辑,内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分:1
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DDS Verilog 代码。包含英文文档说明
DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
- 2022-10-25 06:35:03下载
- 积分:1
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longxin
龙芯CPU+IP+资源简介,希望大家能够了解自己开发的芯片。(Godson CPU+ IP+ Resource profile, hope that we can understand their own chips.)
- 2008-12-10 19:55:39下载
- 积分:1
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这是一个非常实用的,非常实用,关于使用的软件,电动汽车…
这是一个很实用的,很实用的,关于软件的使用,大家可以来看看。-This is a very practical, very practical, with regard to the use of software, everyone can come and see.
- 2023-06-17 10:00:02下载
- 积分:1
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GPS全球定位接收机 原理与软件实现_12378929
本书从电子技术和通信系统的角度讲解gps接收机的设计开发原理,其内容集中在用户终端,即接收机的设计原理和软件实现上。全书分为两大部分,第一部分为理论篇,第二部分为实现篇。理论篇首先对导航的基本目的进行了阐述,并由一个浅显的二维导航系统对导航信号的特点进行了推导,随后阐述了gps信号格式,同时对于直接影响接收机性能的射频前端部分做了理论分析;实现篇主要对本书实现的软件gps接收机的系统实现和源代码进行了讲解,同时作为总结,将信号处理的结果和有意义的中间变量以图示的方式给出,可以使读者有一个感性的认识,同时提升学习兴趣。.
本书适合从事卫星导航接收机研发的技术人员和卫星通信接收机研究的研究人员,尤其是从事北斗系统研发的专业人员、cdma通信系统研发人员,以及通信电子类专业的高年级本科生和研究生阅读,既可作为教学培训的教材,也可作为相关专业工程技术人员的参考资料。(This book explains the design and development principle of the GPS receiver from the perspective of electronic technology and communication system. Its content focuses on the design principle and software implementation of the user terminal, that is, the receiver. The whole book is divided into two parts. The first part is the theoretical part and the second part is the realization part. Firstly, the basic purpose of navigation is expounded, and the characteristics of navigation signal are deduced by a simple two-dimensional navigation system. Then, the format of GPS signal is expounded. At the same time, the front-end part of radio frequency which directly affects the performance of the receiver is theoretically analyzed.)
- 2019-05-05 08:54:24下载
- 积分:1
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OFDM系统中的相位跟踪模块(Phase_Tracking)的FPGA实现
OFDM系统中的相位跟踪模块(Phase_Tracking)的FPGA实现-Phase_Tracking in OFDM sysytems
- 2022-10-06 04:25:03下载
- 积分:1
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led_test
在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA
)
- 2013-08-13 08:55:45下载
- 积分:1
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VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
- 2022-01-20 23:11:51下载
- 积分:1
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RS(204-188)decoder_verilog
采用verilog实现的有限域GF(28)弱对偶基乘法器,本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ,多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7},弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)
- 2016-06-12 16:31:51下载
- 积分:1
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93 std
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
- 2022-02-25 16:35:00下载
- 积分:1