▍1. project
说明: 10M左右的数字频率计,高精度,带有显示屏的显示程序(it is the first time that i give the produce to all of you.i just want to have)
说明: 10M左右的数字频率计,高精度,带有显示屏的显示程序(it is the first time that i give the produce to all of you.i just want to have)
通过一个计数器来实现输出信号的占空比要求,可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
说明: 通过一个计数器来实现输出信号的占空比要求,可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)
说明: quartus vitual jtag代码使用接口,通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)
说明: FPGA应用状态机版,适合初学者学习状态机三段式,ASMD图的理解和翻译,以及Verilog语言的应用 最后对仿真的一些理解 其中包含HDL设计及testbench描述 根据要求设计了一个能求出一个32bit字中两个相邻0之间最大间隙的电路。(FPGA application state machine version, suitable for beginners to learn state machine three-stage, ASMD chart understanding and translation, and Verilog language application. Finally, some understanding of simulation, including HDL design and testbench description According to the requirements, a circuit is designed to find the maximum gap between two adjacent zeros in a 32 bit word.)
说明: 串口程序Verilog语言开发,正点原子的,学习的可以看看(Veriloge en en en ne ne ne ne ne ne ne)
一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)
说明: 一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)
说明: VGA彩条信号显示器设计 设计并调试好一个VGA彩条信号发生器,并用EDA实验开发系统(拟采用的实验芯片的型号可选Altera CycloneII系列的 EP2C5T144C8 FPGA。(A VGA color bar signal generator is designed and debugged, and an EDA experimental development system is used (the model of the experimental chip to be used can be selected as EP2C5T144C8 FPGA of Altera Cyclone II series).)
说明: 接收部分包括HDB3码的解码模块、位同步模块和序列同步模块。其中,HDB3解码模块通过VHDL语言编码恢复原始码型;位同步模块采用了快速位同步法--码元边沿跟踪的方法;序列同步模块采用了灌码序列同步法。(The receiving part included HDB3 code decoding module,bit synchronization module and sequence synchronization module.)
DDS VHDL include everything of dds AD9914
说明: DDS VHDL include everything of dds AD9914
可以实现2PSK的信号调制,已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
说明: 可以实现2PSK的信号调制,已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)
文件用于驱动TFT屏,分辨率800*400,平台为quartus13,芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
说明: 文件用于驱动TFT屏,分辨率800*400,平台为quartus13,芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
FPGA 开发指导书掌握Quartus II文本输入法设计电路的步骤。 (2) 掌握Quartus II混合输入法进行电路层次化设计。 (3) 掌握在 Quartus II 中调用 ModelSim 进行仿真(Grasp the steps of designing circuit with Quartus II text input method. (2) Master Quartus II hybrid input method for hierarchical circuit design. (3) Master calling ModelSim in Quartus II for simulation)
说明: FPGA 开发指导书掌握Quartus II文本输入法设计电路的步骤。 (2) 掌握Quartus II混合输入法进行电路层次化设计。 (3) 掌握在 Quartus II 中调用 ModelSim 进行仿真(Grasp the steps of designing circuit with Quartus II text input method. (2) Master Quartus II hybrid input method for hierarchical circuit design. (3) Master calling ModelSim in Quartus II for simulation)
FPGA控制m25p16flash芯片读写控制spi协议 可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA Erase Write-Read Function)