AHB_to_Wishbone_Verilog

代码说明：

说明：  该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)

文件列表：

AHB_to_Wishbone_Verilog
.......................\bench
.......................\.....\ahb2wb_tb.v,4429,2007-08-01
.......................\doc
.......................\...\ahb_doc.doc,1326080,2007-08-01
.......................\...\ahb_doc.pdf,1820380,2007-08-01
.......................\...\ahb_doc.sxw,1262555,2007-08-01
.......................\sim
.......................\...\modelsim.ini,29876,2007-08-01
.......................\...\run.mti,213,2007-08-01
.......................\src
.......................\...\ahb2wb.v,4105,2007-08-17