AMBA-Bus_Verilog_Model

代码说明：

说明：  该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)

文件列表：

AMBA Bus_Verilog_Model
......................\ahb_apb_bridge
......................\..............\rtl
......................\..............\...\ahb_apb_bridge.v,10636,2010-05-28
......................\ahb_arbiter
......................\...........\rtl
......................\...........\...\ahb_arbiter.v,9321,2010-05-28
......................\...........\...\ahb_decoder.v,3039,2010-05-28
......................\...........\...\ahb_default_master.v,1718,2010-05-28
......................\...........\...\ahb_default_slave.v,4555,2010-05-28
......................\...........\...\ahb_mast_mux.v,3537,2010-05-28
......................\...........\...\ahb_slave_mux.v,2765,2010-05-28
......................\ahb_rom_slave
......................\.............\rtl
......................\.............\...\ahb_rom_slave.v,7167,2010-05-28
......................\ahb_sram_slave
......................\..............\rtl
......................\..............\...\ahb_sram_slave.v,7505,2010-05-28
......................\defines
......................\.......\ahb_defines.v,2295,2010-05-28
......................\.......\apb_defines.v,1144,2010-05-28