verilog_FPGA_DDC

代码说明：

  这是一个用verilog HDL实现的实现数字下变频的源代码。(This is a verilog HDL used to achieve the realization of digital down conversion of the source code.)

文件列表：

lpl
...\ddc.asv
...\ddc.m
...\hs_err_pid1492.log
...\hs_err_pid3008.log
...\hs_err_pid3844.log
...\project_UHF_ddc
...\...............\project_UHF_ddc
...\...............\...............\pepExtractor.prj
...\...............\...............\project_UHF_ddc.ise
...\...............\...............\transcript
...\...............\...............\UHF_ddc.ngc
...\...............\...............\UHF_ddc.ngr
...\...............\...............\UHF_ddc.stx
...\...............\...............\UHF_ddc_tb.vhd
...\...............\...............\UHF_ddc_tb_vhd.fdo
...\...............\...............\UHF_ddc_tb_vhd.udo
...\recv_tb.vhd
...\The MathWorks Deutschland - Filter Design Toolbox - Implementing the Filter Chain of a Digital Down-Converter in HDL Demo.htm
...\htm" target=_blank>transcript
...\第十讲 数字下变频器的FPGA设计实现.ppt