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uartfifo
串口通信例程,使用FIFO数据缓存。Verilog源码,基于FPGA的uart开发,加深理解。(uart communication)
- 2017-04-20 22:16:21下载
- 积分:1
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jiaotongdeng
交通灯控制系统VHDL源码,用VHDL语言、MAXPLUS2环境设计实现(VHDL core)
- 2009-03-05 20:01:07下载
- 积分:1
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e1framerdeframer
E1成帧器和解帧器的FPGA实现源码,测试可用(E1 Framer deframer)
- 2012-12-07 12:10:06下载
- 积分:1
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bt656_decode
将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分:1
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cpu_design
FPGA MIPS架构CPU,五段流水线功能,ISE开发,verilog语言,可综合,模拟结果正确,内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)
- 2020-12-03 13:09:25下载
- 积分:1
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LCD1602测试程序
说明: 实现对LCD1602的Verilog HDL编程(the program for LCD1602 based on Verilog HDL)
- 2020-06-23 21:00:01下载
- 积分:1
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edashuzipinlvji
EDA/VHDL数字频率计,可编程逻辑门阵列,EDA课程设计(EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design)
- 2013-04-16 17:00:58下载
- 积分:1
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FPGA实现四位数与四位数乘法
FPGA实现四位数与四位数乘法,有仿真波形,合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)
- 2020-06-21 00:00:02下载
- 积分:1
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8 位加法器 verilog
嘿,这里是 ise 格式代码为 xilinx 软件 verilog 的 8 位固定点编码使用此编码与测试工作台为例
- 2022-07-01 13:04:00下载
- 积分:1
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4-to-1
4选1数据选择器,有使能端控制,4个数据输入,2个地址端,1个输出(4 1 data selector, enable end control, four data inputs, two addresses end, an output)
- 2012-10-15 18:48:38下载
- 积分:1