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this a fpga sparttan 3e based project in which i have made a game based on vg...

于 2023-09-06 发布文件大小:1.63 kB

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this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the main file included in the project.

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Altera USB声卡
altera usb 下载线DIY完全资料-altera usb blaster

2022-04-29 21:31:03下载

积分：1
verlog hdl brushless motor control procedures have been in ModelSim Simulation
verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation

2022-03-25 00:10:35下载

积分：1
The source code for the Nios II development of an example, the main demonstratio...
本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

2022-06-27 00:21:06下载

积分：1
OFDM
OFDM完美出图，信噪比，16QAM星座图，加窗信号时域和频域波形图(Perfect figure, OFDM SNR, 16 qam constellation diagram, add window signal time domain and frequency domain waveform figure)

2021-04-15 15:08:54下载

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Escalimetro
all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

2012-12-25 02:14:17下载

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my_SMG_Fengzhuang
FPGA 数码管接口例化编程，学习初级入门verilog编程技术(FPGA 数码管接口例化编程)

2015-01-05 20:43:50下载

积分：1
apb_uart
这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)

2021-04-12 14:18:57下载

积分：1
通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，...
通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role

2022-06-02 18:18:30下载

积分：1
waveform_-generator
简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL. )

2011-06-12 21:13:27下载

积分：1
带load、clr等功能的寄存器
带load、clr等功能的寄存器-belt load, the function clr Register

2022-06-20 10:15:42下载

积分：1

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this a fpga sparttan 3e based project in which i have made a game based on vg...

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