-
asynchronous-clock-boundary
一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)
- 2011-12-21 14:30:54下载
- 积分：1
-
8_LigWater
FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序！！(FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !)
- 2012-10-02 11:25:50下载
- 积分：1
-
at96
isa总线接口，可以实现与isa总线 的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)
- 2008-05-15 20:36:51下载
- 积分：1
-
OQPSK
OPSK调制解调。代码思路很清晰，也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)
- 2021-03-09 20:39:27下载
- 积分：1
-
GAL
有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)
- 2013-07-09 22:50:01下载
- 积分：1
-
Adder4
本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的(The design is to design a full adder 4 content, is one of four full adder in series from the)
- 2009-05-11 19:50:58下载
- 积分：1
-
Encode5b_4b
PD里面的4B5B编码，欢迎使用~~~~~~~~~~~~~~~~~(4B5B code in PD3.0 or USB3.0, welcome to use~~~~~~~~~~~~~~)
- 2020-12-03 09:09:25下载
- 积分：1
-
count16
说明： 制作16位流水灯，实现LED模块对于拨杆0和1的识别(Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module)
- 2020-06-24 01:20:02下载
- 积分：1
-
BT1120转GTX详细设计方案
bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)
- 2020-06-25 05:40:02下载
- 积分：1
-
FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
