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一款8位Turbo
一款8位Turbo-51的CPU软核的设计-An 8 Turbo-51" s soft-core CPU design ....
- 2022-02-25 13:52:11下载
- 积分:1
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pluse
说明: 发送两个频段的脉冲 个数和频率均可调
发送两个频段的脉冲 个数和频率均可调(pluse and adjust the width of pluse pluse and adjust the width of pluse )
- 2010-04-14 11:00:03下载
- 积分:1
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master_slave
说明: AXI4-Lite总线的主从机读写,例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
- 2019-03-22 22:24:20下载
- 积分:1
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full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合...
full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
- 2022-06-30 03:26:15下载
- 积分:1
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3Verilog语言要素
说明: Verilog学习文档,介绍基本知识点,语言要素(for learning Verilog)
- 2020-03-24 10:01:15下载
- 积分:1
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胡尚存 iuh h,ggygy dddtr 化为 ytf
hbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu sås jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje
- 2023-02-27 19:30:03下载
- 积分:1
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counter
本例源代码文件由用户按照书中的操作步骤自己生成,“Example-2-1Project_Navigator_Demo源代码”目录下为源代码的参考文件。“Example-2-1Project_Navigator_Democounter”目录下为完整的工程,包括源代码文件、综合与实现的结果文件、ISE工程文件等,可以使用ISE工程管理器打开工程,供读者参考(In this case the source code files by the user in accordance with the steps the book itself is generated, "Example-2-1 Project_Navigator_Demo source" directory as the source code reference document. "Example-2-1 Project_Navigator_Demo counter" directory for a complete project, including source code files, integrated with the realization of the outcome document, ISE project file, etc. You can use ISE Project Manager, open the project for the reader is referred to)
- 2009-09-19 13:53:10下载
- 积分:1
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nios_ruanhe_spi_3
这是我自己写的一个摄像头数据存储SD卡程序,quartus的verilog编写,摄像头采用自己添加的外设接口,数据采用dma采集,SD用的是软件自带的SPI内核以及znFAT的文件系统。帧率我没有测,有兴趣的可以测测,初学者可以参考学习,写的代码有点乱,如果有不懂的可以和联系。(This is what I wrote it myself a camera, SD card data storage program, quartus the verilog write, add their own camera with peripheral interfaces, data acquisition using dma, SD with the software that comes with SPI znFAT kernel and file system. I did not measure the frame rate, are interested can Cece, beginners can refer to the study, wrote the code a bit messy, if there do not understand can contact)
- 2015-09-18 11:39:07下载
- 积分:1
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vhd语言编写交通灯
本代码来自老师指导,自己编写,可以修改交通灯的时间
- 2022-12-15 17:30:09下载
- 积分:1
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此ip核是xvga视频接口控制器,主要针对xilinx公司的开发工具
此ip核是xvga视频接口控制器,主要针对xilinx公司的开发工具-This ip is nuclear XVGA video interface controller, the main target Xilinx
- 2022-01-25 16:44:58下载
- 积分:1