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FPGASquare-RootRaised-CosineFilter
数字通信系统中, 基带信号的频谱一般较宽, 因此
传递前需对信号进行成形处理, 以改善其频谱特性,使
得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分(FPGA Implementation of Square Root Raised Cosine Pulse Shaping Filter)
- 2011-05-04 21:23:36下载
- 积分:1
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matlab
真是基于matlab的QPSK,格雷码,瑞利衰减信道,加性高斯白噪声仿真(Really based on matlab QPSK, Gray code, Rayleigh fading channel additive white Gaussian noise simulation)
- 2021-03-16 22:39:21下载
- 积分:1
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project_first
说明: basys3的数字钟,可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分:1
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verilog8
Learning Verilog Chinese Version Part 8
- 2012-06-15 06:04:00下载
- 积分:1
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en.SPI_EEPROM_Verilog_models_V10
spi接口的eeprom模型,型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)
- 2021-01-19 14:28:44下载
- 积分:1
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verilogsram
FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)
- 2012-11-11 11:41:04下载
- 积分:1
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fir_verilog_matlab
本设计是基于FPGA的一个FIR低通滤波器设计,要求使用Verilog语言编写滤波器模块,通过编译和综合,并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)
- 2014-03-21 09:58:41下载
- 积分:1
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人脸识别(3D)
基于高清视频的3D人脸识别源代码,四万多行,经过FPGA实际验证,最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分:1
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CycloneII_NiosII_2C35_Rev02_DB_SCH
说明: nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)
- 2010-03-28 20:50:27下载
- 积分:1
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FPGA_实时时钟设计
通过配置DS1302芯片来实现实时时钟的监测,我们通过通过控制2个按键来选择我们要在数码管上显示的时间,按下按键1我们来显示周几,按下按键2来显示年月日,不按显示时分秒,这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.)
- 2020-10-22 15:17:23下载
- 积分:1