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专家来告诉你如何进行网站项目的开发控制与管理
专家来告诉你如何进行网站项目的开发控制与管理-experts to tell you how to conduct site project development and management control
- 2022-10-01 02:25:03下载
- 积分：1
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卷积码及其维特比译码算法的软件实现 c语言算法介绍
卷积码及其维特比译码算法的软件实现 c语言算法介绍-Convolutional Codes and Viterbi decoding algorithm software algorithm introduced language c
- 2023-01-24 14:15:04下载
- 积分：1
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演示在ODBC中使用时间日期
演示在ODBC中使用时间日期-ODBC demonstration in the use of time-of-day
- 2022-01-28 07:01:27下载
- 积分：1
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The majority of the basic situation of the mobile to find a job for a friend, it...
移动基本情况 适合广大找工作的朋友，很难弄到啊-The majority of the basic situation of the mobile to find a job for a friend, it is difficult to get ah
- 2022-12-24 02:25:03下载
- 积分：1
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介绍3dmax的书籍，从头开始，讲的比较详细，值得一看
介绍3dmax的书籍，从头开始，讲的比较详细，值得一看-introduced 3dmax books, and start from scratch, say in greater detail, an eye-catcher
- 2023-04-21 19:35:03下载
- 积分：1
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acm大赛题，
acm大赛题，-acm contest that, well good
- 2022-10-21 11:35:04下载
- 积分：1
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JavaTM 2 Platform Standard Edition 5.0
API 规范
JavaTM 2 Platform Standard Edition 5.0
API 规范 -JavaTM 2 Platform Standard Edition 5.0 API norms
- 2023-01-26 17:35:07下载
- 积分：1
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西安交通大学做的那个道路检测系统的资料，希望对大家有帮助...
西安交通大学做的那个道路检测系统的资料，希望对大家有帮助-Xi" an Jiaotong University to do that road detection system, the information you want to help
- 2023-04-24 11:45:03下载
- 积分：1
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Java用户界面编程指南，着重讲述了如何用java设计出精美的界面，对java程序员来说有特别的意义。...
Java用户界面编程指南，着重讲述了如何用java设计出精美的界面，对java程序员来说有特别的意义。-Java user interface programming guide, will focus on how to use java beautifully designed interface, the java programmer is of special significance.
- 2022-01-26 08:33:40下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
