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ahb_sramc_svtb
ahb总线Verilog代码及sv仿真文件(ahb bus Verilog code and sv simulation code)
- 2021-05-14 14:30:02下载
- 积分：1
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ddr3_mig8
fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)
- 2018-01-18 21:05:12下载
- 积分：1
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reference
早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)
- 2015-04-30 15:06:04下载
- 积分：1
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用vlog语言编制程序CPU控制器源代码…
用vlog语言编写的cpu控制器源代码，用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
- 2022-02-15 12:37:59下载
- 积分：1
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一篇关于FIFO设计以及FPGA设计的文章
一篇关于FIFO设计以及FPGA设计的文章-FIFO 1 on the design and FPGA design article
- 2022-11-02 11:35:03下载
- 积分：1
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verilog 比较基础的教程 呵呵 新手学习学习啊 大家有资料工乡
verilog 比较基础的教程 呵呵 新手学习学习啊 大家有资料工乡-basis of comparison of the tutorial Verilog Ha ha ah novice learn Rural U.S. Data Works
- 2023-08-29 03:10:03下载
- 积分：1
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pcf8563
pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)
- 2013-12-24 21:46:21下载
- 积分：1
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本例为电子琴VHDL程序原代码,电子琴,可实现基本功能
本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of
- 2022-03-23 15:59:38下载
- 积分：1
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mydesign
基于FPGA的直接序列扩频发射机的设计与仿真。实验中以QuartusII 7.2 为设计和仿真工具，
各模块采用Verilog HDL设计并封装，顶层使用图形设计方式,最后得到的仿真结果使用Matlab描点来绘制出波形。
(FPGA-based direct sequence spread spectrum transmitter of the design and simulation. Experiment to QuartusII 7.2 for the design and simulation tools, the module using Verilog HDL to design and package, the top-level use of graphic design, and finally the simulation results obtained using the Matlab description points to draw waveforms.)
- 2009-06-30 13:18:09下载
- 积分：1
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shift example
shift example for verilog
- 2018-12-18 05:24:04下载
- 积分：1
