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all clock
说明： 数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:01下载
- 积分：1
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多进制数字频率调制(MFSK)系统VHDL程序
多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures
- 2022-04-13 12:32:15下载
- 积分：1
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16_QAM
用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)
- 2013-09-02 16:23:40下载
- 积分：1
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Copy
说明： this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device
- 2020-06-21 21:00:02下载
- 积分：1
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用verilog实现FSK调制，称为IP核来实现模块…
用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
- 2022-03-15 17:40:05下载
- 积分：1
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Blazing-Fiber-grating
闪耀光栅
有带阻滤波器作用的闪耀光纤光栅，反射角度可以控制(Blazed grating)
- 2021-03-27 09:19:12下载
- 积分：1
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Verilog-SRAM
用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)
- 2020-12-09 15:39:18下载
- 积分：1
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beep_interface
这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)
- 2013-05-05 21:07:18下载
- 积分：1
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rams
combinatorial modules
- 2019-04-13 19:41:21下载
- 积分：1
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在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。...
在Quartus环境中，采用VHDL语言编写的出租车计费系统，系统共分为分频、状态切换、记程、计费等模块，模仿现实中出租车计费。-In the Quartus environment, the use of VHDL language taxi billing system, the system is divided into sub-frequency, state switching, recording process, billing and other modules, to imitate reality, taxi billing.
- 2022-02-25 18:59:33下载
- 积分：1
