登录
首页 » Verilog » IQ解调器

IQ解调器

于 2023-05-28 发布 文件大小:168.09 kB
0 199
下载积分: 2 下载次数: 1

代码说明:

我必须做智商演示项目。我不知道写代码verilog.so版本请提供matlab和verilog在fpga中的编码实施iq解调器由以下模块组成:射频调制信号、混频器、低通过滤.it包含同相分量、正交分量。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • i2c_reader
    一个采用IIC协议,从ROM里面读数据的接口程序,采用verilog语言,状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)
    2013-07-31 09:25:56下载
    积分:1
  • Huffman_enc_dec
    Huffman encoder decoder verilog
    2021-03-21 00:49:17下载
    积分:1
  • pinlvji
    频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C(Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C)
    2020-10-30 20:39:55下载
    积分:1
  • tcd1209d
    TCD1209D驱动程序 Verilog语言(TCD1209D driver Verilog language)
    2021-04-08 09:49:01下载
    积分:1
  • MIPS_32位
    32位单周期校验码
    2022-04-01 11:56:32下载
    积分:1
  • -Elliptic
    We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.
    2012-02-09 10:48:50下载
    积分:1
  • 浮动点加法器
    语言代码编码中用于添加 2 xilinx 浮点数...... 和此编码中使用的技术是 piplining......
    2022-09-16 23:30:03下载
    积分:1
  • 16bit-Mulitiplier-Verilog-procedure
    这是一个16位乘法器Verilog程序,包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)
    2012-12-25 11:33:48下载
    积分:1
  • clk_generator
    时钟分频代码,PWM产生 RTL 源代码。(clock divider,PWM generator RTL Source Code)
    2013-08-18 09:29:42下载
    积分:1
  • PWM
    说明:  脉冲宽度调制,VHDL代码编写,包括QUARTUSII和MODELSIM工程以及testbench(Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench)
    2020-11-26 09:49:31下载
    积分:1
  • 696518资源总数
  • 106182会员总数
  • 24今日下载