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Verilog code for RS
Verilog code for RS-(255,239) encoder.
- 2022-02-02 19:13:13下载
- 积分:1
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fen pin qi
半整数分频器的实现(verilog),本文以6.5分频为例!很实用的!-fen pin qi
- 2022-02-01 02:05:40下载
- 积分:1
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06219426Spartan3E
VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)
- 2011-02-10 09:41:12下载
- 积分:1
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其基于FIFO的设计
its a Fifo BASED design
i also Interface DAC2904
- 2023-02-01 15:35:04下载
- 积分:1
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UART VHDL Quartus
uart的vhdl实现,包含完整quartus工程文件,相信会有较大帮助-uart vhdl quartus
- 2022-03-13 00:29:53下载
- 积分:1
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这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用...
这时一个数字钟的VHDL程序,有计时、校时、整点报时功能,很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
- 2022-05-22 23:36:04下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
- 2022-11-12 18:25:03下载
- 积分:1
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实验九 计算机核心(CPU+RAM)的设计与实现
计算机组成原理的CPU实验,基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)
- 2018-06-09 11:13:43下载
- 积分:1
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-------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is par
---- ----
---- WISHBONE Wishbone_BFM IP Core ----
---- ----
---- This file is part of the Wishbone_BFM project ----
---- http://www.opencores.org/cores/Wishbone_BFM/ ----
---- ----
---- Description ----
---- Implementation of Wishbone_BFM IP core according to ----
---- Wishbone_BFM IP core specification document.---------
---- WISHBONE Wishbone_BFM IP Core----
--------
---- This file is part of the Wishbone_BFM project----
---- http://www.opencores.org/cores/Wishbone_BFM/----
--------
---- Description----
---- Implementation of Wishbone_BFM IP core according to----
---- Wishbone_BFM IP core specification document.
- 2022-05-26 15:36:06下载
- 积分:1
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Quartus中实现的DDS 使用的是altera提供的IP core
Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
- 2022-07-12 10:39:19下载
- 积分:1