-
74ls138-integral-4-wire-encoder-16
74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)
- 2011-09-20 19:00:59下载
- 积分:1
-
针对于Virtex5FPGA的DDR2读写测试的完整工程
资源描述针对于Virtex5FPGA的DDR2读写测试的完整工程,已测试可以使用,可以根据自己的ddr2配置自行更改。。。。
- 2023-02-19 21:40:05下载
- 积分:1
-
du to fpga 4*4 keyscan verilog
基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog
- 2022-01-25 20:49:28下载
- 积分:1
-
T13_USB
本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输,实现了pc端接收来自FPGA开发板的数据,并显示条纹,具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)
- 2011-01-05 15:10:38下载
- 积分:1
-
FPGA源代码
FPGA源代码公布,包括多进制数字频率调制VHDL程序FPGA驱动LCD显示中文字符“年”程序,LED静态显示ADC0809 VHDL控制程序,DAC0832 接口电路程序
- 2022-04-26 16:23:11下载
- 积分:1
-
test bench for alu 6 functions
test bench for alu 6 functions
- 2022-03-02 06:50:51下载
- 积分:1
-
Nios-II
数字电路的设计。以软件方式实现硬件电路,功能强大,开发容易。(Digital circuit design. With software to realize the hardware circuit, powerful, development easy.
)
- 2011-12-03 09:47:56下载
- 积分:1
-
LED-clock-display
利用单片机控制LED时钟显示,以及闹钟,程序较大,但比较简单易懂。(LED clock display)
- 2013-03-10 10:15:37下载
- 积分:1
-
016_versat_updown_counter
说明: Verilog实现的加减法功能计数器,通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
- 2019-11-27 23:16:27下载
- 积分:1
-
VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
VHDL_COUNTING 0_9_LED 7 段 (ĐẾM 0 ĐẾN 9 HIỂN THỊ LED 7 ĐOẠN BẰNG NGÔN NGỮ VHDL)
- 2022-02-11 16:15:23下载
- 积分:1