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mybch1
说明： 实现（7,4）BCH码的编码和译码。已知生成矩阵和校验矩阵，通过c=m*G进行编码，译码时利用伴随式译码。s=c*H‘，求得伴随式，对应的错误图样找到错误位置，对错误位置进行更正，得到译码结果。(Coding and decoding of (7,4) BCH Codes)
- 2021-04-27 17:28:44下载
- 积分：1
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MIPSTOP
misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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project_1
简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分：1
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TRY-1516-CSV0115--- SANGEETHA
VHDL BASED DATA COMPRESSION
- 2019-01-01 16:37:53下载
- 积分：1
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ECC密码体制在VHDL
这段代码是用VHDL解释椭圆曲线密码术的。这段代码包含了使用FPGA板进行ECC加密的必要算法！ ；
- 2023-08-26 09:45:04下载
- 积分：1
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tcoug
Synopsys®
Timing Constraints and Optimization
User Guide
- 2014-08-23 17:37:56下载
- 积分：1
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costas
载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
)
- 2021-03-05 13:09:31下载
- 积分：1
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chuankou
说明： 本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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8BIT_CPU
一个8位的CPU设计，用verilog语言写的，希望有用(A CPU OF 8 BITS
)
- 2020-07-01 09:00:02下载
- 积分：1
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EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分：1
