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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号,在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯,数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分:1
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CORDIC算法的FFT实现
本代码实现了 ; ;CORDIC ; 算法语言;
- 2022-09-09 16:25:03下载
- 积分:1
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Datasheets
关于ALTERA DE2板上的文档资料,包括应用实例,用户文档和板上常用器件的技术文档(datasheets of ALTERA DE2)
- 2010-03-10 10:14:08下载
- 积分:1
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fenpinqi de vhdlchengxu gongnengfnagzhen,政
分频器的VHDL程序,完整的建立工程,编译,功能功能仿真,验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
- 2022-02-21 21:03:34下载
- 积分:1
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i2c
uboot i2c driver code for arm a5 dual core cpu imapx820, which is an soc of infotmic.
- 2012-10-18 21:51:29下载
- 积分:1
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VGAPPS2PCORDIC
FPGA课程设计源码,整合VGA,PS2键盘,CORDIC三角函数算法,在basys2平台上使用完全可行。(FPGA curriculum design source, integrated VGA, PS2 keyboard, CORDIC trigonometric algorithm, used on basys2 platform entirely feasible.)
- 2015-10-12 20:56:05下载
- 积分:1
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decoder_38
这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)
- 2013-08-04 09:53:07下载
- 积分:1
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gcounter1
数字钟vhdl实现,在线测试无误,具有闹钟,对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)
- 2013-10-19 22:06:16下载
- 积分:1
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hls_bluebook
非常好的catapult学习书, catabult 可用于高级综合,由c产生vhdl/verilog(very nice book for catabult study)
- 2011-08-18 16:15:08下载
- 积分:1
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temperature-control-system.zip
a microcontroller as the core of the vegetable greenhouse temperature control system.
- 2013-06-02 20:30:05下载
- 积分:1